From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ih3du-0002Db-S6 for qemu-devel@nongnu.org; Sun, 14 Oct 2007 09:36:30 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ih3dt-0002Cd-SL for qemu-devel@nongnu.org; Sun, 14 Oct 2007 09:36:30 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ih3dt-0002CP-JI for qemu-devel@nongnu.org; Sun, 14 Oct 2007 09:36:29 -0400 Received: from pop-gadwall.atl.sa.earthlink.net ([207.69.195.61]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ih3dt-00027q-Gl for qemu-devel@nongnu.org; Sun, 14 Oct 2007 09:36:29 -0400 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-gadwall.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1Ih3do-0006fQ-00 for qemu-devel@nongnu.org; Sun, 14 Oct 2007 09:36:24 -0400 Message-ID: <47121B58.2060206@earthlink.net> Date: Sun, 14 Oct 2007 09:36:24 -0400 From: Robert Reif MIME-Version: 1.0 Subject: Re: [Qemu-devel] [RFC] sparc32 MXCC support References: <47112DFE.4050600@earthlink.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Blue Swirl wrote: >On 10/13/07, Robert Reif wrote: > > >>I'm trying to add SuperSparc II MXCC support and need some feedback. >> >>Is there a better way to read and write physical memory in 64bit chunks? >>I'm not sure what I'm doing is portable between 32/64 and big/little endian. >> >> > >Thank you for your effort. Applying the patch allows NetBSD on SS-10 >to boot as far as on SS-5, previously it crashed. > >I think the code is portable, but I think changing the register type >to uint32_t and using a DPRINTF system like used in for example >hw/iommu.c should make the code slightly clearer. > I don't have access to chip specs but from reading linux and *bsd code it appears that the registers are 64 bits wide but sometimes accessed as 32 bits to get only the bottom 32 bits. Do you mean using two uint32_t for a 64 bit register? How about a union of 2 uint32_t and a uint64_t. Is that portable? Never mind. I just found out there is an ldq_phys and stq_phys. I'll use those. I looked at DPRINTF but would need a DPRINTF_MMU and DPRINTF_MXCC ... Would that be acceptable? > >For the memory access, ldl/q_phys/stl/q_phys is used in other block >copy routines. For longer blocks or if the address can be unaligned, >cpu_physical_memory_read() could be a better choice. > > > > >>+int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, int cpu); >> >> > >unsigned int cpu? > > OK >>+ printf("ERROR: helper_ld_asi(asi = %d, size = %d, sign = %d) T0 = %08x: unsupported size\n", asi, size, sign, T0); >> >> > >If it's an error to access the registers with different size, you >should use do_unassigned_access() to report this. > > > These are more for me to make sure I catch all the necessary accesses without adding unnecessary code. linux 2.4 and netbsd only use the ones I have implemented. openboot uses more and also some undocumented ones which are caught by this but I don't know how to handle them yet. I will use do_unassigned_access where necessary now. Thanks for the review.