From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ih8Ij-0002Vl-FN for qemu-devel@nongnu.org; Sun, 14 Oct 2007 14:34:57 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ih8Ie-0002NF-Or for qemu-devel@nongnu.org; Sun, 14 Oct 2007 14:34:56 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ih8Ie-0002N0-Kf for qemu-devel@nongnu.org; Sun, 14 Oct 2007 14:34:52 -0400 Received: from pop-siberian.atl.sa.earthlink.net ([207.69.195.71]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ih8Ie-0003f1-Fq for qemu-devel@nongnu.org; Sun, 14 Oct 2007 14:34:52 -0400 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-siberian.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1Ih8Id-0000P4-00 for qemu-devel@nongnu.org; Sun, 14 Oct 2007 14:34:51 -0400 Message-ID: <4712614B.9050908@earthlink.net> Date: Sun, 14 Oct 2007 14:34:51 -0400 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060408010806040409030800" Subject: [Qemu-devel] [PATCH] sparc32 use stq_* for 64bit stores Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------060408010806040409030800 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Use stq_* for 64 bit stores. This fixes one bug where T1 was used twice rather than T1 and T2. Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3? Should these unaligned address cause traps? --------------060408010806040409030800 Content-Type: text/plain; name="stq.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="stq.diff.txt" Index: target-sparc/op_helper.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.44 diff -p -u -r1.44 op_helper.c --- target-sparc/op_helper.c 14 Oct 2007 17:07:21 -0000 1.44 +++ target-sparc/op_helper.c 14 Oct 2007 18:28:37 -0000 @@ -515,8 +515,7 @@ void helper_st_asi(int asi, int size) stl_user(T0 & ~3, T1); break; case 8: - stl_user(T0 & ~3, T1); - stl_user((T0 + 4) & ~3, T2); + stq_user(T0 & ~3, ((uint64_t)T1 << 32) | T2); break; } break; @@ -533,8 +532,7 @@ void helper_st_asi(int asi, int size) stl_kernel(T0 & ~3, T1); break; case 8: - stl_kernel(T0 & ~3, T1); - stl_kernel((T0 + 4) & ~3, T2); + stq_kernel(T0 & ~3, ((uint64_t)T1 << 32) | T2); break; } break; @@ -591,8 +589,7 @@ void helper_st_asi(int asi, int size) stl_phys(T0 & ~3, T1); break; case 8: - stl_phys(T0 & ~3, T1); - stl_phys((T0 + 4) & ~3, T2); + stq_phys(T0 & ~3, ((uint64_t)T1 << 32) | T2); break; } } @@ -615,10 +612,8 @@ void helper_st_asi(int asi, int size) | ((target_phys_addr_t)(asi & 0xf) << 32), T1); break; case 8: - stl_phys((target_phys_addr_t)(T0 & ~3) - | ((target_phys_addr_t)(asi & 0xf) << 32), T1); - stl_phys((target_phys_addr_t)((T0 + 4) & ~3) - | ((target_phys_addr_t)(asi & 0xf) << 32), T1); + stq_phys((target_phys_addr_t)(T0 & ~3) + | ((target_phys_addr_t)(asi & 0xf) << 32), ((uint64_t)T1 << 32) | T2); break; } } --------------060408010806040409030800--