From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IpXyf-00029t-Vk for qemu-devel@nongnu.org; Tue, 06 Nov 2007 18:37:02 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IpXye-000282-IN for qemu-devel@nongnu.org; Tue, 06 Nov 2007 18:37:01 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IpXye-00027a-1S for qemu-devel@nongnu.org; Tue, 06 Nov 2007 18:37:00 -0500 Received: from pop-siberian.atl.sa.earthlink.net ([207.69.195.71]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IpXyc-0007q6-80 for qemu-devel@nongnu.org; Tue, 06 Nov 2007 18:36:58 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-siberian.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1IpXyX-0001ND-00 for qemu-devel@nongnu.org; Tue, 06 Nov 2007 18:36:53 -0500 Message-ID: <4730FA92.1050108@earthlink.net> Date: Tue, 06 Nov 2007 18:36:50 -0500 From: Robert Reif MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] sparc32 boot mode flag fix References: <472FD561.7020006@earthlink.net> In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org >>This patch also performs a CPU reset after the CPU is registered rather >>than before. >> >> > >Why is this change needed? > > > Reset should be doing CPU dependent stuff and the CPU dependent setup is performed when the CPU is registered.