From: "H. Peter Anvin" <hpa@zytor.com>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>,
William Lee Irwin III <wli@holomorphy.com>,
Andi Kleen <ak@suse.de>, Ingo Molnar <mingo@elte.hu>,
Thomas Gleixner <tglx@linutronix.de>,
Nick Piggin <nickpiggin@yahoo.com.au>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: Why preallocate pmd in x86 32-bit PAE?
Date: Thu, 15 Nov 2007 14:42:46 -0800 [thread overview]
Message-ID: <473CCB66.2080601@zytor.com> (raw)
In-Reply-To: <alpine.LFD.0.9999.0711151403000.4260@woody.linux-foundation.org>
Linus Torvalds wrote:
>
> IIRC, the present bit is ignored in the magic 4-entry PGD. All entries
> have to be present.
>
This is true, although you could point a PGD to an all-zero page if you
really wanted to. You have to re-load CR3 after modifying the top-level
entries.
> What earlier CPU's did was to basically load all four values into the CPU
> when you loaded %cr3. There was no "three-level page table walker" at all:
> it was still a two-level page table walker, there were just for magic
> internal page tables that were indexed off the two high bits.
They still are. Loading CR3 in PAE really loads four registers from
memory. x86-64 is different, of course.
-hpa
next prev parent reply other threads:[~2007-11-15 22:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-11-15 21:57 Why preallocate pmd in x86 32-bit PAE? Jeremy Fitzhardinge
2007-11-15 22:12 ` Linus Torvalds
2007-11-15 22:42 ` H. Peter Anvin [this message]
2007-11-16 0:40 ` William Lee Irwin III
2007-11-16 0:41 ` H. Peter Anvin
2007-11-16 11:16 ` Andi Kleen
2007-11-16 15:45 ` H. Peter Anvin
2007-11-16 15:53 ` Andi Kleen
2007-11-16 16:10 ` H. Peter Anvin
2007-11-16 17:12 ` Jeremy Fitzhardinge
2007-11-16 17:35 ` Linus Torvalds
2007-11-16 18:30 ` Jeremy Fitzhardinge
2007-11-16 19:14 ` Jeremy Fitzhardinge
2007-11-16 19:22 ` Linus Torvalds
2007-11-16 19:43 ` Jeremy Fitzhardinge
2007-11-16 17:45 ` H. Peter Anvin
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