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Date: Sun, 18 Nov 2007 16:58:38 -0500
From: Robert Reif <reif@earthlink.net>
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Subject: Re: [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order
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To: qemu-devel@nongnu.org

Blue Swirl wrote:

>On 11/18/07, Robert Reif <reif@earthlink.net> wrote:
>  
>
>>Blue Swirl wrote:
>>
>>    
>>
>>>On 11/16/07, Robert Reif <reif@earthlink.net> wrote:
>>>
>>>
>>>      
>>>
>>>>>This patch fixes the word order for 64 bit reads of the mxcc registers.
>>>>>
>>>>>
>>>>>          
>>>>>
>>>Otherwise everything seems OK, but it breaks NetBSD version 3 on SS10:
>>>clock0 at obio0 slot 0 offset 0x200000: mk48t08
>>>timer0 at obio0 slot 0 offset 0x300000data fault: pc=0xf0111a0c
>>>addr=0x0 sfsr=126<PERR=0,LVL=1,AT=1,FT=1,FAV,OW>
>>>panic: kernel fault
>>>halted
>>>
>>>halt, power off
>>>
>>>Without the patch I get:
>>>clock0 at obio0 slot 0 offset 0x200000: mk48t08
>>>timer0 at obio0 slot 0 offset 0x300000: delay constant 99
>>>zs0 at obio0 slot 0 offset 0x100000 level 12 softpri 6
>>>zstty0 at zs0 channel 0 (console i/o)
>>>zstty1 at zs0 channel 1
>>>scsi-disk: Unsupported command length, command 79
>>>
>>>
>>>
>>>
>>>
>>>      
>>>
>>This is a classic case of two wrongs make a right.  OpenBios need to be
>>fixed to set mbus module id to start at 8, not 0 for mbus based machines.
>>    
>>
>
>Turbosparc manual says that the module id is hardwired to 0x8, so
>would it be OK if mid was  i + 8 for all machines?
>
>
>
>  
>
Probably but I don't know for sure.  I just fired up a SPARCclassic X 
which has a microSPARC CPU and the mid was 0.  You may need to check the 
CPU type for the SS5.  I don't have the time right now to dig out a 
microSPARC SS5 to check it out.