From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IuI9C-0007oo-H9 for qemu-devel@nongnu.org; Mon, 19 Nov 2007 20:43:30 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IuI99-0007m1-T2 for qemu-devel@nongnu.org; Mon, 19 Nov 2007 20:43:30 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IuI99-0007ls-QJ for qemu-devel@nongnu.org; Mon, 19 Nov 2007 20:43:27 -0500 Received: from pop-savannah.atl.sa.earthlink.net ([207.69.195.69]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IuI99-0000Mv-AV for qemu-devel@nongnu.org; Mon, 19 Nov 2007 20:43:27 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-savannah.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1IuI97-0006m0-00 for qemu-devel@nongnu.org; Mon, 19 Nov 2007 20:43:25 -0500 Message-ID: <47423BBD.9040905@earthlink.net> Date: Mon, 19 Nov 2007 20:43:25 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------020901090001030408090609" Subject: [Qemu-devel] [PATCH] sparc32 MMU fixes Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------020901090001030408090609 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch adds support for some more MMU registers: 0x10 TLB replacement control 0x13 read/write access to 0x03 SFSR 0x14 read/write access to 0x04 SFAR Only support for 1 real register was added (0x10) but 16 were added to CPUSPARCState because we don't check for invalid register accesses yet. Different CPUs use different registers and there isn't enough documentation to work out what is valid or not so we just waste some space. This patch also preserves the bits we are not interested in for tlb flushing in the processor control register (0x00). --------------020901090001030408090609 Content-Type: text/plain; name="mmu.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="mmu.diff.txt" Index: target-sparc/cpu.h =================================================================== RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v retrieving revision 1.58 diff -p -u -r1.58 cpu.h --- target-sparc/cpu.h 10 Nov 2007 15:15:54 -0000 1.58 +++ target-sparc/cpu.h 20 Nov 2007 01:23:33 -0000 @@ -215,7 +215,7 @@ typedef struct CPUSPARCState { uint64_t dtlb_tag[64]; uint64_t dtlb_tte[64]; #else - uint32_t mmuregs[16]; + uint32_t mmuregs[32]; uint64_t mxccdata[4]; uint64_t mxccregs[8]; #endif Index: target-sparc/op_helper.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.57 diff -p -u -r1.57 op_helper.c --- target-sparc/op_helper.c 19 Nov 2007 19:14:10 -0000 1.57 +++ target-sparc/op_helper.c 20 Nov 2007 01:23:33 -0000 @@ -248,11 +248,15 @@ void helper_ld_asi(int asi, int size, in break; case 4: /* read MMU regs */ { - int reg = (T0 >> 8) & 0xf; + int reg = (T0 >> 8) & 0x1f; ret = env->mmuregs[reg]; if (reg == 3) /* Fault status cleared on read */ - env->mmuregs[reg] = 0; + env->mmuregs[3] = 0; + else if (reg == 0x13) /* Fault status read */ + ret = env->mmuregs[3]; + else if (reg == 0x14) /* Fault address read */ + ret = env->mmuregs[4]; DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret); } break; @@ -493,17 +497,18 @@ void helper_st_asi(int asi, int size) } case 4: /* write MMU regs */ { - int reg = (T0 >> 8) & 0xf; + int reg = (T0 >> 8) & 0x1f; uint32_t oldreg; oldreg = env->mmuregs[reg]; switch(reg) { case 0: - env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm); - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm); + env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | + (T1 & 0x00ffffff); // Mappings generated during no-fault mode or MMU // disabled mode are invalid in normal mode - if (oldreg != env->mmuregs[reg]) + if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) != + (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm))) tlb_flush(env, 1); break; case 2: @@ -517,6 +522,12 @@ void helper_st_asi(int asi, int size) case 3: case 4: break; + case 0x13: + env->mmuregs[3] = T1; + break; + case 0x14: + env->mmuregs[4] = T1; + break; default: env->mmuregs[reg] = T1; break; --------------020901090001030408090609--