From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IuhHO-00076T-Tj for qemu-devel@nongnu.org; Tue, 20 Nov 2007 23:33:38 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IuhHO-000763-De for qemu-devel@nongnu.org; Tue, 20 Nov 2007 23:33:38 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IuhHO-000760-5h for qemu-devel@nongnu.org; Tue, 20 Nov 2007 23:33:38 -0500 Received: from pop-canoe.atl.sa.earthlink.net ([207.69.195.66]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IuhHN-0003X8-T9 for qemu-devel@nongnu.org; Tue, 20 Nov 2007 23:33:37 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-canoe.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1IuhHM-0002gf-00 for qemu-devel@nongnu.org; Tue, 20 Nov 2007 23:33:36 -0500 Message-ID: <4743B51F.30303@earthlink.net> Date: Tue, 20 Nov 2007 23:33:35 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------090808050806030609050609" Subject: [Qemu-devel] [PATCH] sparc32 iommu fix Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------090808050806030609050609 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Set initial value of AFSR register properly. --------------090808050806030609050609 Content-Type: text/plain; name="iommu.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="iommu.diff.txt" Index: hw/iommu.c =================================================================== RCS file: /sources/qemu/qemu/hw/iommu.c,v retrieving revision 1.19 diff -p -u -r1.19 iommu.c --- hw/iommu.c 17 Nov 2007 17:14:42 -0000 1.19 +++ hw/iommu.c 21 Nov 2007 04:30:28 -0000 @@ -311,6 +311,7 @@ static void iommu_reset(void *opaque) s->iostart = 0; s->regs[IOMMU_CTRL] = s->version; s->regs[IOMMU_ARBEN] = IOMMU_MID; + s->regs[IOMMU_AFSR] = 0x00800000; } void *iommu_init(target_phys_addr_t addr, uint32_t version) --------------090808050806030609050609--