Re: Init hangs on Xilinx4

[schardt <g.schardt@fz-juelich.de>]

David H. Lynch Jr. wrote:
> I had a similar problem. In my instance it turned out that I was
> inadvertently using the physical address of my uart as the output address.
> This worked during boot becasue there was a 1:1 physical-logical entry
> stuffed into the MMU. But since Linux did nto know about it, as soon as
> the VM system decided to use that TLB entry IO died - right in the
> middle of a string.
>
> While it is unlikely you made exactly the same mistake. One area you can
> check is memory.
>
> What is your output device ?
>
>   
My Output Device is a Xilinx UartLite at 0x40600000 and the kernel
detects this
as /dev/ttyUL0.

Georg







-------------------------------------------------------------------
-------------------------------------------------------------------
Forschungszentrum Jülich GmbH
52425 Jülich

Sitz der Gesellschaft: Jülich
Eingetragen im Handelsregister des Amtsgerichts Düren Nr. HR B 3498
Vorsitzende des Aufsichtsrats: MinDirig'in Bärbel Brumme-Bothe
Geschäftsführung: Prof. Dr. Achim Bachem (Vorsitzender),
Dr. Ulrich Krafft (stellv. Vorsitzender), Dr. Sebastian M. Schmidt
-------------------------------------------------------------------
-------------------------------------------------------------------