From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2008 16:35:47 +0000 (GMT) Received: from wa-out-1112.google.com ([209.85.146.182]:15128 "EHLO wa-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20032276AbYAHQfi (ORCPT ); Tue, 8 Jan 2008 16:35:38 +0000 Received: by wa-out-1112.google.com with SMTP id m16so12130548waf.20 for ; Tue, 08 Jan 2008 08:35:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date:mime-version:content-type:x-mailer:thread-index:x-mimeole:message-id; bh=PELyFxm5PzJ8bpyBey4ewQLTaqF2L2dyzKngfH4i5zU=; b=oVwHwUOqHnHvqilEYPPCFAJp8Gwy60Ll+Im5Q7jDJoFrfXIRl9tgV1rEqUwUWygglYrTKdR0NBQ/CutRLXR5oE1BTn636XbRDKtww+iT12I9LZDmoWrdWCup6juqEvuvVaYk83IVTSkn0oU8KPwg/9h80Gg+xVxi+JBfHTjFurc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:mime-version:content-type:x-mailer:thread-index:x-mimeole:message-id; b=Zzi7Mhr9JczG7ahWmPXq13c/C0Zjzg91sCcSg9RW2RHenNBdAUsBG8ohyLRpf/IaF6Me4abT0VkNGYWU5n2R2kmKDbjgLxTEzatv5WhimpWBAKhfbMPph2fGhrj0Cv8Zllszpfsvfsh/fGsdz4DspRHt/w1VHXKkvVrZZbnOa3k= Received: by 10.115.74.1 with SMTP id b1mr455677wal.93.1199810131289; Tue, 08 Jan 2008 08:35:31 -0800 (PST) Received: from WWW8E1E968C4DF ( [124.78.172.63]) by mx.google.com with ESMTPS id m28sm33925040poh.7.2008.01.08.08.35.29 (version=SSLv3 cipher=RC4-MD5); Tue, 08 Jan 2008 08:35:30 -0800 (PST) From: "lovecentry" To: Subject: kseg1 uncache access issue Date: Wed, 9 Jan 2008 00:35:06 +0800 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0004_01C85257.7C6BA180" X-Mailer: Microsoft Office Outlook, Build 11.0.5510 Thread-Index: AchSFGznFIKi14IwSXqLn9eejUkhaA== X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3198 Message-ID: <4783a652.1cef600a.2530.fffffe31@mx.google.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 17954 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lovecentry@gmail.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------=_NextPart_000_0004_01C85257.7C6BA180 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi As we know in mips achitecture if current pc falls into kseg1 segment, any memory reference will bypass cache and fetch directly from dram. But for some prcoessor such like mips R10K it has off chip L2 cache. I haven't found any available path which can access dram directly. All memory reference need pass through L2 cache. Does it mean any memory reference in kseg1 will be fetch from L2 cache rather than dram for such system? How does such system design when system software need access kseg1 region? Further more, Kseg2 is used to do memory map for those peripheral so Is there has a particular circuit that routes those access to the appropriate destination. Any suggestion is highly appreciate!!! Tony ------=_NextPart_000_0004_01C85257.7C6BA180 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi<= /span>

As we know in = mips achitecture if current pc falls into kseg1 segment, any memory reference = will bypass cache and fetch directly from dram. But for some prcoessor such = like mips R10K it has off chip L2 cache. I haven't found any available path = which can access dram directly. All memory reference need pass through L2 = cache. Does it mean any memory reference in kseg1 will be fetch from L2 cache rather = than dram for such system? How does such system design when system software = need access kseg1 region? Further more, Kseg2 is used to do memory map for = those peripheral so Is there has a particular circuit that routes those access to the = appropriate destination.

Any = suggestion is highly appreciate!!!

 

Tony

=
------=_NextPart_000_0004_01C85257.7C6BA180-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wa-out-1112.google.com ([209.85.146.182]:15128 "EHLO wa-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20032276AbYAHQfi (ORCPT ); Tue, 8 Jan 2008 16:35:38 +0000 Received: by wa-out-1112.google.com with SMTP id m16so12130548waf.20 for ; Tue, 08 Jan 2008 08:35:37 -0800 (PST) From: "lovecentry" Subject: kseg1 uncache access issue Date: Wed, 9 Jan 2008 00:35:06 +0800 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0004_01C85257.7C6BA180" Message-ID: <4783a652.1cef600a.2530.fffffe31@mx.google.com> Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org To: linux-mips@linux-mips.org Message-ID: <20080108163506.Q3Uxt8afbtK6WJ8MdpGXf5h3br5wNjmyhRptnn-8p3w@z> This is a multi-part message in MIME format. ------=_NextPart_000_0004_01C85257.7C6BA180 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi As we know in mips achitecture if current pc falls into kseg1 segment, any memory reference will bypass cache and fetch directly from dram. But for some prcoessor such like mips R10K it has off chip L2 cache. I haven't found any available path which can access dram directly. All memory reference need pass through L2 cache. Does it mean any memory reference in kseg1 will be fetch from L2 cache rather than dram for such system? How does such system design when system software need access kseg1 region? Further more, Kseg2 is used to do memory map for those peripheral so Is there has a particular circuit that routes those access to the appropriate destination. Any suggestion is highly appreciate!!! Tony ------=_NextPart_000_0004_01C85257.7C6BA180 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi<= /span>

As we know in = mips achitecture if current pc falls into kseg1 segment, any memory reference = will bypass cache and fetch directly from dram. But for some prcoessor such = like mips R10K it has off chip L2 cache. I haven't found any available path = which can access dram directly. All memory reference need pass through L2 = cache. Does it mean any memory reference in kseg1 will be fetch from L2 cache rather = than dram for such system? How does such system design when system software = need access kseg1 region? Further more, Kseg2 is used to do memory map for = those peripheral so Is there has a particular circuit that routes those access to the = appropriate destination.

Any = suggestion is highly appreciate!!!

 

Tony

=
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