Re: [Qemu-devel] [PATCH 1/5] Fix i386 Host

[Alexander Graf <alex@csgraf.de>]

[-- Attachment #1: Type: text/plain, Size: 266 bytes --]

Alexander Graf wrote:
> This patch is mostly a cleanup of Michael Matz's patch with the ideas
> that came last time included.
>
>   
I didn't include one file in the previous patch, sorry.
This patch also includes Johannes' catch to use #ifdefs around most changes.

[-- Attachment #2: qemu-gcc4-i386.patch --]
[-- Type: text/x-patch, Size: 6523 bytes --]

Index: qemu/softmmu_header.h
===================================================================
--- qemu.orig/softmmu_header.h
+++ qemu/softmmu_header.h
@@ -189,9 +189,15 @@ static inline void glue(glue(st, SUFFIX)
 #else
 #error unsupported size
 #endif
+#ifdef GCC_BREAKS_T_REGISTER
+                  "pushl %%ecx\n"
+#endif
                   "pushl %6\n"
                   "call %7\n"
                   "popl %%eax\n"
+#ifdef GCC_BREAKS_T_REGISTER
+                  "popl %%ecx\n"
+#endif
                   "jmp 2f\n"
                   "1:\n"
                   "addl 8(%%edx), %%eax\n"
@@ -209,14 +215,22 @@ static inline void glue(glue(st, SUFFIX)
                   : "r" (ptr),
 /* NOTE: 'q' would be needed as constraint, but we could not use it
    with T1 ! */
+#if DATA_SIZE == 1 || DATA_SIZE == 2
+                  "q" (v),
+#else
                   "r" (v),
+#endif
                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
                   "i" (CPU_MMU_INDEX),
                   "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
+#ifdef GCC_BREAKS_T_REGISTER
+                  : "%eax", "%edx", "memory", "cc");
+#else
                   : "%eax", "%ecx", "%edx", "memory", "cc");
+#endif
 }
 
 #else
Index: qemu/target-alpha/cpu.h
===================================================================
--- qemu.orig/target-alpha/cpu.h
+++ qemu/target-alpha/cpu.h
@@ -275,6 +275,8 @@ struct CPUAlphaState {
      * used to emulate 64 bits target on 32 bits hosts
      */
     target_ulong t0, t1, t2;
+#elif defined(GCC_BREAKS_T_REGISTER)
+    target_ulong t2;
 #endif
     /* */
     double ft0, ft1, ft2;
Index: qemu/target-alpha/exec.h
===================================================================
--- qemu.orig/target-alpha/exec.h
+++ qemu/target-alpha/exec.h
@@ -40,7 +40,11 @@ register struct CPUAlphaState *env asm(A
 
 register uint64_t T0 asm(AREG1);
 register uint64_t T1 asm(AREG2);
+#ifdef GCC_BREAKS_T_REGISTER
+#define T2 (env->t2)
+#else
 register uint64_t T2 asm(AREG3);
+#endif
 
 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 
Index: qemu/target-arm/cpu.h
===================================================================
--- qemu.orig/target-arm/cpu.h
+++ qemu/target-arm/cpu.h
@@ -66,6 +66,9 @@ typedef uint32_t ARMReadCPFunc(void *opa
  */
 
 typedef struct CPUARMState {
+#if defined(GCC_BREAKS_T_REGISTER)
+    uint32_t t2;
+#endif
     /* Regs for current mode.  */
     uint32_t regs[16];
     /* Frequently accessed CPSR bits are stored separately for efficiently.
Index: qemu/target-arm/exec.h
===================================================================
--- qemu.orig/target-arm/exec.h
+++ qemu/target-arm/exec.h
@@ -23,7 +23,12 @@
 register struct CPUARMState *env asm(AREG0);
 register uint32_t T0 asm(AREG1);
 register uint32_t T1 asm(AREG2);
+#ifdef GCC_BREAKS_T_REGISTER
+#define T2 (env->t2)
+#else
 register uint32_t T2 asm(AREG3);
+#endif
+
 
 /* TODO: Put these in FP regs on targets that have such things.  */
 /* It is ok for FT0s and FT0d to overlap.  Likewise FT1s and FT1d.  */
Index: qemu/target-i386/cpu.h
===================================================================
--- qemu.orig/target-i386/cpu.h
+++ qemu/target-i386/cpu.h
@@ -470,6 +470,8 @@ typedef struct CPUX86State {
 #if TARGET_LONG_BITS > HOST_LONG_BITS
     /* temporaries if we cannot store them in host registers */
     target_ulong t0, t1, t2;
+#elif defined(GCC_BREAKS_T_REGISTER)
+    target_ulong t1;
 #endif
 
     /* standard registers */
Index: qemu/target-i386/exec.h
===================================================================
--- qemu.orig/target-i386/exec.h
+++ qemu/target-i386/exec.h
@@ -44,7 +44,11 @@ register struct CPUX86State *env asm(ARE
 /* XXX: use unsigned long instead of target_ulong - better code will
    be generated for 64 bit CPUs */
 register target_ulong T0 asm(AREG1);
+#ifdef GCC_BREAKS_T_REGISTER
+#define T1 (env->t1)
+#else
 register target_ulong T1 asm(AREG2);
+#endif
 register target_ulong T2 asm(AREG3);
 
 /* if more registers are available, we define some registers too */
Index: qemu/target-mips/cpu.h
===================================================================
--- qemu.orig/target-mips/cpu.h
+++ qemu/target-mips/cpu.h
@@ -149,6 +149,8 @@ struct CPUMIPSState {
     target_ulong t0;
     target_ulong t1;
     target_ulong t2;
+#elif defined(GCC_BREAKS_T_REGISTER)
+    target_ulong t2;
 #endif
     target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
     target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
Index: qemu/target-mips/exec.h
===================================================================
--- qemu.orig/target-mips/exec.h
+++ qemu/target-mips/exec.h
@@ -17,8 +17,12 @@ register struct CPUMIPSState *env asm(AR
 #else
 register target_ulong T0 asm(AREG1);
 register target_ulong T1 asm(AREG2);
+#ifdef GCC_BREAKS_T_REGISTER
+#define T2 (env->t2)
+#else
 register target_ulong T2 asm(AREG3);
 #endif
+#endif
 
 #if defined (USE_HOST_FLOAT_REGS)
 #error "implement me."
Index: qemu/target-ppc/exec.h
===================================================================
--- qemu.orig/target-ppc/exec.h
+++ qemu/target-ppc/exec.h
@@ -41,7 +41,11 @@ register struct CPUPPCState *env asm(ARE
 #else
 register unsigned long T0 asm(AREG1);
 register unsigned long T1 asm(AREG2);
+#if GCC_BREAKS_T_REGISTER
+#define T2 (env->t2)
+#else
 register unsigned long T2 asm(AREG3);
+#endif
 #define TDX "%016lx"
 #endif
 /* We may, sometime, need 64 bits registers on 32 bits targets */
Index: qemu/target-sparc/exec.h
===================================================================
--- qemu.orig/target-sparc/exec.h
+++ qemu/target-sparc/exec.h
@@ -32,10 +32,14 @@ register uint32_t T2 asm(AREG4);
 
 #else
 #define REGWPTR env->regwptr
+#ifdef HOST_I386
+#define T2 (env->t2)
+#else
 register uint32_t T2 asm(AREG3);
-#endif
 #define reg_T2
 #endif
+#endif
+#endif
 
 #define FT0 (env->ft0)
 #define FT1 (env->ft1)
Index: qemu/dyngen-exec.h
===================================================================
--- qemu.orig/dyngen-exec.h
+++ qemu/dyngen-exec.h
@@ -90,6 +90,9 @@ extern int printf(const char *, ...);
 #define NULL 0
 
 #if defined(__i386__)
+#if __GNUC__ > 3
+#define GCC_BREAKS_T_REGISTER
+#endif
 #define AREG0 "ebp"
 #define AREG1 "ebx"
 #define AREG2 "esi"