From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xavian-Anderson Macpherson Subject: Re: [PATCH] Disable Xen PowerNow! support on Opteron 2nd gen and earlier processors Date: Fri, 25 Jan 2008 15:31:07 -0800 Message-ID: <479A713B.5040507@comcast.net> References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0437270042==" Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Mime-version: 1.0 Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org This is a multi-part message in MIME format. --===============0437270042== Content-Type: multipart/alternative; boundary="------------000300050908010708030208" This is a multi-part message in MIME format. --------------000300050908010708030208 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Are we in fact talking about the new Barcelona chips? If so, their frequency settings are independent per core. Unless I have misunderstood the question. Shingoshi Keir Fraser wrote: > On 25/1/08 22:58, "Mark Langsdorf" wrote: > > >> I tried this suggestion and also implemented the trace function in >> cpu_frequency_change() and local_time_calibration() you suggested in >> a previous message. >> >> It made no discernable difference in my tests. I did high to low >> and low to high changes roughly every five minutes, and always got >> an excessive difference inside of Xen and usually got error messages >> in Linux. >> > > It's a bit confusing as to what is going on since there are 4 CPUs in the > system. Are arbitrary or all CPUs changing frequency, or just one of them? > Is the single-step PSTATE_CTRL MSR being used, or the multi-step FID_VID > method where voltage adjustments are under software control? What is the > system's CPU topology, and do any of the cores have their frequency controls > tied together? > > It'd be useful to have each tracing line stamped with the CPU that it comes > from. As it is the tracing looks very suspect because the systimes on > adjacent lines are much less than one second, and calibration is supposed to > happen no more than once per second. > > -- Keir > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > > --------------000300050908010708030208 Content-Type: multipart/related; boundary="------------090202070406010809010507" --------------090202070406010809010507 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Are we in fact talking about the new Barcelona chips? If so, their frequency settings are independent per core. Unless I have misunderstood the question.

Shingoshi

Keir Fraser wrote:

On 25/1/08 22:58, "Mark Langsdorf" <mark.langsdorf@amd.com> wrote:

I tried this suggestion and also implemented the trace function in
cpu_frequency_change() and local_time_calibration() you suggested in
a previous message.

It made no discernable difference in my tests.  I did high to low
and low to high changes roughly every five minutes, and always got
an excessive difference inside of Xen and usually got error messages
in Linux.


It's a bit confusing as to what is going on since there are 4 CPUs in the
system. Are arbitrary or all CPUs changing frequency, or just one of them?
Is the single-step PSTATE_CTRL MSR being used, or the multi-step FID_VID
method where voltage adjustments are under software control? What is the
system's CPU topology, and do any of the cores have their frequency controls
tied together?

It'd be useful to have each tracing line stamped with the CPU that it comes
from. As it is the tracing looks very suspect because the systimes on
adjacent lines are much less than one second, and calibration is supposed to
happen no more than once per second.

 -- Keir



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Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel

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