From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from buildserver.ru.mvista.com (unknown [85.21.88.6]) by ozlabs.org (Postfix) with ESMTP id 50140DDF09 for ; Tue, 25 Mar 2008 01:08:07 +1100 (EST) Message-ID: <47E7B61B.70708@ru.mvista.com> Date: Mon, 24 Mar 2008 17:09:31 +0300 From: Sergei Shtylyov MIME-Version: 1.0 To: Grant Likely Subject: Re: [PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx uart 16550. References: <12060242324116-git-send-email-john.linn@xilinx.com> <20080320144402.3063517C005D@mail148-sin.bigfish.com> <18403.32257.725539.470771@cargo.ozlabs.ibm.com> In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Cc: linuxppc-dev@ozlabs.org, Paul Mackerras , John Linn List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Grant Likely wrote: >> > Personally, I'm not fond of this approach. There is already some >> > traction to using the reg-shift property to specify spacing, and I >> > think it would be appropriate to also define a reg-offset property to >> > handle the +3 offset and then let the xilinx 16550 nodes use those. >> Why do we need a reg-offset property when we can just add the offset >> to the appropriate word(s) in the reg property? > Primarily because the device creates 32 byte registers starting at 0; > but they are also big-endian byte accessible so a byte read at offset > 8 also works. Probably I misunderstood you: does it give the same result as offset 11? > reg-offset seems to be a better description of the hardware to me. Have you considered using the existing "big-endian" property? > Cheers, > g. WBR, Sergei