From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from buildserver.ru.mvista.com (unknown [85.21.88.6]) by ozlabs.org (Postfix) with ESMTP id 8AAFEDE180 for ; Tue, 25 Mar 2008 04:02:20 +1100 (EST) Message-ID: <47E7DEF1.9050501@ru.mvista.com> Date: Mon, 24 Mar 2008 20:03:45 +0300 From: Sergei Shtylyov MIME-Version: 1.0 To: Sergei Shtylyov Subject: Re: [PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx uart 16550. References: <12060242324116-git-send-email-john.linn@xilinx.com> <20080320144402.3063517C005D@mail148-sin.bigfish.com> <18403.32257.725539.470771@cargo.ozlabs.ibm.com> <47E7B61B.70708@ru.mvista.com> <47E7D3BB.1050403@ru.mvista.com> In-Reply-To: <47E7D3BB.1050403@ru.mvista.com> Content-Type: text/plain; charset=us-ascii; format=flowed Cc: linuxppc-dev@ozlabs.org, Paul Mackerras , John Linn List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi, I wrote: > Oh, well... unfortunately, we can't use UPIO_MEM32 "register model" > in 8250.c anyway since that makes use of readl()/writel() -- which treat > the bus as bigendian on PPC... anyway, we would need at least a I was going to write "as little-endian"... :-< > "reg-size" property, if not new "compatible"... WBR, Sergei