From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: Laurent Pinchart <laurentp@cse-semaphore.com>
Cc: linuxppc-dev@ozlabs.org,
MTD mailing list <linux-mtd@lists.infradead.org>,
Trent Piepho <xyzzy@speakeasy.org>
Subject: Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings
Date: Tue, 01 Apr 2008 17:04:18 +0400 [thread overview]
Message-ID: <47F232D2.9040200@ru.mvista.com> (raw)
In-Reply-To: <200804011439.04905.laurentp@cse-semaphore.com>
Laurent Pinchart wrote:
>>>On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:
>>>>> p) Freescale Synchronous Serial Interface
>>>>>- q) USB EHCI controllers
>>>>>+ q) USB EHCI controllers
>>>>>+ r) Memory-mapped RAM & ROM
>>>> Memory-mapped RA/RO Memory again? Should better drop this. :-)
>>>You're quite picky, aren't you ? :-)
>>>I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Auxiliary
>>>RAM & ROM" ?
>>Direct-mapped?
> Fine with me. Sergei ?
I agree. The only thing that somewhat worries me it that it will have no
"compatible" prop...
WBR, Sergei
next prev parent reply other threads:[~2008-04-01 13:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-03-31 16:39 [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings Laurent Pinchart
2008-03-31 16:39 ` Laurent Pinchart
2008-03-31 17:06 ` Sergei Shtylyov
2008-03-31 17:06 ` Sergei Shtylyov
2008-04-01 8:47 ` Laurent Pinchart
2008-04-01 8:47 ` Laurent Pinchart
2008-04-01 9:18 ` Trent Piepho
2008-04-01 9:18 ` Trent Piepho
2008-04-01 12:39 ` Laurent Pinchart
2008-04-01 12:39 ` Laurent Pinchart
2008-04-01 13:04 ` Sergei Shtylyov [this message]
2008-04-01 13:16 ` Grant Likely
2008-04-03 10:15 ` Laurent Pinchart
2008-04-03 10:15 ` Laurent Pinchart
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