From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH][RFC]Move PCI Configuration Spaces from Dom0 toXen Date: Fri, 11 Apr 2008 14:08:10 +0200 Message-ID: <47FF70CA.76E4.0078.0@novell.com> References: <823A93EED437D048963A3697DB0E35DE01427E60@pdsmsx414.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <823A93EED437D048963A3697DB0E35DE01427E60@pdsmsx414.ccr.corp.intel.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Haitao Shan Cc: Kevin Tian , xen-devel , Allen M Kay , Yunhong Jiang , Weidong Han , Keir Fraser List-Id: xen-devel@lists.xenproject.org >>> "Shan, Haitao" 10.04.08 11:45 >>> >Hi, Keir, > >This patch will move reading and writing of PCI configuration spaces >from dom0 to Xen. It also changes VTD code, so that they can touch the >PCI configuration spaces with proper lock. >This will also benefit MSI support in Xen. >Can you give some comments? Thanks! > <>=20 I don't think this is going to do what you want when the kernel is using mmconfig, or AMD's extended register space access method (not to speak of the hopefully not in wide spread use type 2 access method). Also I find it a little odd that you allow access to ports cf9...cfb = rather than properly handling namely byte accesses to cf9. Likewise it doesn't consider the (albeit unlikely) case of multi-byte accesses to ports crossing the cf8/cfc boundary. Jan