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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id ta14-20020a1709078c0e00b00949c02dcf10sm2808780ejc.6.2023.04.07.23.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 23:14:12 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Jagan Teki , Andre Przywara Cc: Samuel Holland , Piotr Oniszczuk , Mikhail Kalashnikov , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 1/2] sunxi: boot0.h: allow RVBAR MMIO address customisation Date: Sat, 08 Apr 2023 08:14:11 +0200 Message-ID: <4818131.31r3eYUQgx@jernej-laptop> In-Reply-To: <20230405142731.1246503-1-andre.przywara@arm.com> References: <20230405142731.1246503-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Dne sreda, 05. april 2023 ob 16:27:30 CEST je Andre Przywara napisal(a): > To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need > to program the 64-bit start code address into an MMIO mapped register > that shadows the architectural RVBAR register. > This address is SoC specific, with just two versions out there so far. > Now a third address emerged, on a *variant* of an existing SoC (H616). > > Change the boot0.h start code to make this address a Kconfig > selectable option, to allow easier maintenance. > We make this address user-visible (even though it shouldn't be), to > allow putting this in defconfig. This is needed because there are > apparently revisions of the H616 SoC out there using different > addresses, so this becomes a per-board decision. > > Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Best regards, Jernej > --- > arch/arm/include/asm/arch-sunxi/boot0.h | 7 ++----- > arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++ > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h > b/arch/arm/include/asm/arch-sunxi/boot0.h index 46b7e073b59..59ea75a96b5 > 100644 > --- a/arch/arm/include/asm/arch-sunxi/boot0.h > +++ b/arch/arm/include/asm/arch-sunxi/boot0.h > @@ -39,11 +39,8 @@ > .word 0xf57ff06f // isb sy > .word 0xe320f003 // wfi > .word 0xeafffffd // b @wfi > -#ifndef CONFIG_SUN50I_GEN_H6 > - .word 0x017000a0 // writeable RVBAR mapping address > -#else > - .word 0x09010040 // writeable RVBAR mapping address > -#endif > + > + .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr > #ifdef CONFIG_SPL_BUILD > .word CONFIG_SPL_TEXT_BASE > #else > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > index 6417aee944b..b46667ce01e 100644 > --- a/arch/arm/mach-sunxi/Kconfig > +++ b/arch/arm/mach-sunxi/Kconfig > @@ -110,6 +110,18 @@ config SUNXI_SRAM_ADDRESS > Some newer SoCs map the boot ROM at address 0 instead and move the > SRAM to a different address. > > +config SUNXI_RVBAR_ADDRESS > + hex "RVBAR address" > + depends on ARM64 > + default 0x09010040 if SUN50I_GEN_H6 > + default 0x017000a0 > + ---help--- > + The read-only RVBAR system register holds the address of the first > + instruction to execute after a reset. Allwinner cores provide a > + writable MMIO backing store for this register, to allow to set the > + entry point when switching to AArch64. This store is on different > + addresses, depending on the SoC. > + > config SUNXI_A64_TIMER_ERRATUM > bool