SMC921x: problems with LAN9215i connected to i.MX31

[Jens Gehrlein <sew_s@tqs.de>]

Hi,

on our board we connected a LAN9215i to the Freescale i.MX31 ARM 
processor. Bus width: 16 bits. No DMA. Kernel 2.6.22. Driver: smc911x.c 
plus patches since then. Both processor and ethernet controller in 
little endian mode.

Ethereal showed scrambled or shifted data in the Ethernet frame. I 
couldn't identify a certain scheme.

I think, this is caused by the macros SMC_PULL_DATA (-> __raw_writesl 
and SMC_PUSH_DATA (-> __raw_readsl) to read/write the FIFOs. Single word 
accesses, e.g. identifying the controller are okay.

I temporarily replaced the macros by simple copy routines in C, which 
access the chip using 32 bit pointers. The processor automatically 
converts the word in two 16 bit accesses. And voila, it works. 
Unfortunately, I had to insert udelay(1) between each word :-(

Has somebody experience/tested with this processor/ethernet controller 
combination?

Does somebody know, how the assembler routines 
__raw_readsl/__raw_writesl work, so that analysis becomes easier? I 
didn't find any documentation.

What's the state of the new smsc driver Steve Glendinning announced some 
days ago on this list? A first look showed that it uses these assembler 
routines, too.

Thanks and best regards,
Jens


P.S.: is line wrapping okay (Thunderbird)?