From: "Andrew E. Mileski" <andrewm@isoar.ca>
To: linux-mtd@lists.infradead.org
Subject: BCH for NAND ECC
Date: Tue, 03 Jun 2008 18:50:10 -0400 [thread overview]
Message-ID: <4845CAA2.3070207@isoar.ca> (raw)
Is anyone looking at BCH for NAND ECC? If so, I'll let the experts have
at it.
Otherwise...
I can't really find any examples for NAND usage, and am inching my way
through the theory.
Am I correct in that BCH(2096, 2048, 9) would do for 4 correctable
errors in a 256 byte block? Assuming I understand any of it, that would
be 6 bytes of ECC per block.
--
Andrew E. Mileski
reply other threads:[~2008-06-03 22:52 UTC|newest]
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