Keir Fraser wrote:
> On 13/6/08 16:46, "Jean Guyader" <jean.guyader@eu.citrix.com> wrote:
> 
>> +    /* Do we come from AMD processor ? */
>> +    if ( data->msr_flags == -1ULL )
>> +    {
>> +        data->msr_flags = 0x7ULL;
>> +
>> +        data->ldtr_limit = 0xffffffff;
>> +        data->ldtr_arbytes = 0xc00;
>> +
>> +        data->cs_arbytes = 0xc9b;
>> +
>> +        data->gs_limit = 0xffffffff;
>> +        data->gs_arbytes = 0xc00;
>> +
>> +        data->tr_arbytes = 0x8b;
>> +    }
>> +
> 
> It's a bit rude to trample register state like this. Why do limits need to
> be forced? The Intel manuals do not specify that any vm-entry checks are
> applied to segment limits outside of vm86 mode.
> 

Agreed. The vm-entry check was failing on this one (Intel 3b, 22-11):

  - Bit 15 (G). The following checks apply if the register is CS or if 
the register is usable:
    - If any bit in the limit field in the range 11:0 is 0, G must be 0. 

    - If any bit in the limit field in the range 31:20 is 1, G must be 1.

-- 
Jean Guyader