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From: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
To: zhenyu.z.wang@intel.com
Cc: Dave Airlie <airlied@redhat.com>, LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets
Date: Wed, 18 Jun 2008 10:26:10 +0300	[thread overview]
Message-ID: <4858B892.8080909@movial.fi> (raw)
In-Reply-To: <20080618052300.GA16715@zhen-devel.sh.intel.com>

Zhenyu Wang wrote:
> Dave, here's the patch against current git master.
> 
> Thanks.
> 
> [AGP] intel_agp: Add support for Intel 4 series chipsets
> 
> Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
> ---
>  drivers/char/agp/intel-agp.c |   82 ++++++++++++++++++++++++++++++++++++-----
>  1 files changed, 72 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
> index eeea50a..76731db 100644
> --- a/drivers/char/agp/intel-agp.c
> +++ b/drivers/char/agp/intel-agp.c
> @@ -34,6 +34,12 @@
>  #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
>  #define PCI_DEVICE_ID_INTEL_IGD_HB          0x2A40
>  #define PCI_DEVICE_ID_INTEL_IGD_IG          0x2A42
> +#define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
> +#define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
> +#define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
> +#define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
> +#define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
> +#define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
>  
>  /* cover 915 and 945 variants */
>  #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
> @@ -55,6 +61,10 @@
>  		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
>  		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
>  
> +#define IS_G4X	(agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
> +                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
> +                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
> +
>  extern int agp_memory_reserved;
>  
>  
> @@ -80,8 +90,12 @@ extern int agp_memory_reserved;
>  #define I915_PTEADDR	0x1C
>  #define I915_GMCH_GMS_STOLEN_48M	(0x6 << 4)
>  #define I915_GMCH_GMS_STOLEN_64M	(0x7 << 4)
> -#define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
> -#define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
> +#define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
> +#define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
> +#define INTEL_GMCH_GMS_STOLEN_96M	(0xa << 4)
> +#define INTEL_GMCH_GMS_STOLEN_160M	(0xb << 4)
> +#define INTEL_GMCH_GMS_STOLEN_224M	(0xc << 4)
> +#define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4)
>  #define I915_IFPADDR    0x60
>  
>  /* Intel 965G registers */
> @@ -504,6 +518,10 @@ static void intel_i830_init_gtt_entries(void)
>  			size = 512;
>  		}
>  		size += 4;
> +	} else if (IS_G4X) {
> +		/* On 4 Series hardware, GTT stolen is seperate from graphics

You have a spelling error here. Should be "separate".

Thanks,
Dmitri

  reply	other threads:[~2008-06-18  7:25 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-06-18  5:23 [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets Zhenyu Wang
2008-06-18  7:26 ` Dmitri Vorobiev [this message]
2008-06-18  7:34   ` Zhenyu Wang
2008-06-19  0:55     ` Zhenyu Wang
2008-06-19  0:56       ` Zhenyu Wang

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