On MPC52xx the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by: Andre Schwarz --- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner