[U-Boot-Users] Freescale MPC8349EMDS hang on boot

[Jerry Van Baren <gerald.vanbaren@ge.com>]

Ira Snyder wrote:
> On Thu, Jul 17, 2008 at 04:54:53PM -0500, Kim Phillips wrote:
>> On Wed, 16 Jul 2008 15:28:21 -0700
>> Ira Snyder <iws@ovro.caltech.edu> wrote:
>>
>>> During the development, I noticed that adding and removing certain
>>> pieces of debugging code (which did not change any program state) caused
>>> the board to hang on boot, like so:

[snip]

> 
> Hello Kim,
> 
> Thanks for looking at this problem so quickly. I'll try reverting the
> patch as soon as I'm done writing this email and post the results here.
> 
> I spent this afternoon trying to narrow down the problem exhibited by
> the changes in my earlier email. I managed to narrow it down to the
> .data section's start address being a multiple of 32 bytes, and the
> bcsr code in checkboard().
> 
> I have attached a patch which causes my board to hang on boot in exactly
> the same way that the earlier patch does. Removing the line from the
> linker script makes the board boot perfectly, as long as the .data
> section's start address is not on a 32 byte boundary by coincidence.
> 
> Ira
> 
> 
> 
> diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
> index 9a312c3..f4792a9 100644
> --- a/board/freescale/mpc8349emds/mpc8349emds.c
> +++ b/board/freescale/mpc8349emds/mpc8349emds.c
> @@ -165,6 +165,13 @@ int fixed_sdram(void)
>  
>  int checkboard (void)
>  {
> +	volatile immap_t *immr = (immap_t *)CFG_IMMR;
> +	volatile u8 *bcsr = (u8 *)CFG_BCSR;
> +	int in_pci_slot;
> +
> +	/* in a pci slot or standalone */
> +	in_pci_slot = (bcsr[10] & 0x80) ? 1 : 0;
> +
>  	puts("Board: Freescale MPC8349EMDS\n");
>  	return 0;
>  }
> diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds
> index 99ad675..f605eab 100644
> --- a/cpu/mpc83xx/u-boot.lds
> +++ b/cpu/mpc83xx/u-boot.lds
> @@ -79,6 +79,7 @@ SECTIONS
>    __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
>    __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
>  
> +  . = ALIGN(32);
>    .data    :
>    {
>      *(.data)

Hi Ira,

This is a long shot, but could there be a problem with the DDR SDRAM 
and/or its initialization?  Are you using a factory-provided DIMM?  What 
if you try a different one (preferably a different brand/size)?

I'm not familiar with the board configuration, I presume instruction 
caches are enabled.  Are data caches enabled too?  What happens if you 
disable cache(s)?

Best regards,
gvb