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Thus we only need to evade the delayed vblank. LGTM Reviewed-by: Chaitanya Kumar Borah > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_vblank.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c > index 28d81199792e..72e04c4f0303 100644 > --- a/drivers/gpu/drm/i915/display/intel_vblank.c > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c > @@ -724,10 +724,10 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, > * undelayed vblank, so with seamless M/N and LRR we must evade > * both vblanks. > * > - * DSB execution waits for the transcoder's undelayed vblank, > - * hence we must kick off the commit before that. > + * Chained DSB execution waits for the transcoder's undelayed > + * vblank, hence we must kick off the commit before that. > */ > - if (intel_color_uses_dsb(new_crtc_state) || > + if (intel_color_uses_chained_dsb(new_crtc_state) || > new_crtc_state->update_m_n || new_crtc_state->update_lrr) > evade->min -= vblank_delay; > }