From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KWaNa-0002fv-3b for qemu-devel@nongnu.org; Fri, 22 Aug 2008 13:24:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KWaNY-0002fc-Ar for qemu-devel@nongnu.org; Fri, 22 Aug 2008 13:24:53 -0400 Received: from [199.232.76.173] (port=50386 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KWaNY-0002fZ-8h for qemu-devel@nongnu.org; Fri, 22 Aug 2008 13:24:52 -0400 Received: from wr-out-0506.google.com ([64.233.184.234]:64409) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KWaNY-0006GV-2k for qemu-devel@nongnu.org; Fri, 22 Aug 2008 13:24:52 -0400 Received: by wr-out-0506.google.com with SMTP id c46so565963wra.18 for ; Fri, 22 Aug 2008 10:24:51 -0700 (PDT) Message-ID: <48AEF636.9030901@codemonkey.ws> Date: Fri, 22 Aug 2008 12:24:06 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 3/3] [x86] SYSENTER/SYSEXIT IA-32e implementation v3 References: <48AEC1A3.1010502@suse.de> In-Reply-To: <48AEC1A3.1010502@suse.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Alexander Graf wrote: > On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch > makes both 64-bit aware and enables them for Intel CPUs. > > Changes since v1: Add cpu save/load for 64-bit wide sysenter variables > > Signed-off-by: Alexander Graf > > > Index: qemu/target-i386/machine.c > =================================================================== > --- qemu.orig/target-i386/machine.c > +++ qemu/target-i386/machine.c > @@ -88,9 +88,9 @@ void cpu_save(QEMUFile *f, void *opaque) > cpu_put_seg(f, &env->gdt); > cpu_put_seg(f, &env->idt); > > - qemu_put_be32s(f, &env->sysenter_cs); > - qemu_put_be32s(f, &env->sysenter_esp); > - qemu_put_be32s(f, &env->sysenter_eip); > + qemu_put_bels(f, &env->sysenter_cs); > + qemu_put_bels(f, &env->sysenter_esp); > + qemu_put_bels(f, &env->sysenter_eip); What exactly is be1s? Don't you mean be64s? > > qemu_put_betls(f, &env->cr[0]); > qemu_put_betls(f, &env->cr[2]); > @@ -169,7 +169,7 @@ int cpu_load(QEMUFile *f, void *opaque, > int32_t a20_mask; > > if (version_id != 3 && version_id != 4 && version_id != 5 > - && version_id != 6) > + && version_id != 6 && version_id != 7) > return -EINVAL; > for(i = 0; i < CPU_NB_REGS; i++) > qemu_get_betls(f, &env->regs[i]); > @@ -244,8 +244,13 @@ int cpu_load(QEMUFile *f, void *opaque, > cpu_get_seg(f, &env->idt); > > qemu_get_be32s(f, &env->sysenter_cs); > - qemu_get_be32s(f, &env->sysenter_esp); > - qemu_get_be32s(f, &env->sysenter_eip); > + if (version_id >= 7) { > + qemu_get_bels(f, &env->sysenter_esp); > + qemu_get_bels(f, &env->sysenter_eip); > Same here. This doesn't compile, does it? > + } else { > + qemu_get_be32s(f, &env->sysenter_esp); > + qemu_get_be32s(f, &env->sysenter_eip); > + } > > qemu_get_betls(f, &env->cr[0]); > qemu_get_betls(f, &env->cr[2]); Regards, Anthony Liguori