Re: [PATCH 2/6] TXx9: Microoptimize interrupt handlers

[Sergei Shtylyov <sshtylyov@ru.mvista.com>]

Hello.

Atsushi Nemoto wrote:

> The IOC interrupt status register on RBTX49XX only have 8 bits.  Use
> 8-bit version of __fls() to optimize interrupt handlers.
>   

   But doesn't the patch also change the result of 
toshiba_rbtx49{27|38}_irq_nested() if the register reads back as 0?

> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> ---
>  arch/mips/txx9/rbtx4927/irq.c   |    6 +++---
>  arch/mips/txx9/rbtx4938/irq.c   |    8 ++++----
>  include/asm-mips/txx9/generic.h |   18 ++++++++++++++++++
>  3 files changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
> index 22076e3..9c14ebb 100644
> --- a/arch/mips/txx9/rbtx4927/irq.c
> +++ b/arch/mips/txx9/rbtx4927/irq.c
> @@ -133,9 +133,9 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
>  	u8 level3;
>  
>  	level3 = readb(rbtx4927_imstat_addr) & 0x1f;
> -	if (level3)
> -		sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
> -	return sw_irq;
> +	if (unlikely(!level3))
> +		return -1;
> +	return RBTX4927_IRQ_IOC + __fls8(level3);
>  }
>  
>  static void __init toshiba_rbtx4927_irq_ioc_init(void)
> diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
> index ca2f830..7d21bef 100644
> --- a/arch/mips/txx9/rbtx4938/irq.c
> +++ b/arch/mips/txx9/rbtx4938/irq.c
> @@ -85,10 +85,10 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
>  	u8 level3;
>  
>  	level3 = readb(rbtx4938_imstat_addr);
> -	if (level3)
> -		/* must use fls so onboard ATA has priority */
> -		sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
> -	return sw_irq;
> +	if (unlikely(!level3))
> +		return -1;
> +	/* must use fls so onboard ATA has priority */
> +	return RBTX4938_IRQ_IOC + __fls8(level3);
>  }
>  
>  static void __init

WBR, Sergei