SMTC Patches [0 of 3]

["Kevin D. Kissell" <kevink@paralogos.com>]

I've managed to steal enough time to rework the SMTC support
for the MIPS 34K (and, I suppose 1004K) processors so that it
works again near the head of the source tree.  This involved
a complete rework of the clocking model to be compatible with
new common timing event system, which finally enables "tickless"
operation in SMTC, something it needed pretty badly.  I also
solved the problem with using the "wait_irqoff" idle loop
under SMTC.

There are going to be three patches that will follow.  The
first two are relatively localized fixes to problems with
FPU affinity and with IPI replay that I came across in testing
the new code.  The last is a pretty big patch, but it all
pretty much hangs together and I couldn't see any sensible
way to partition it.

	Regards,

	Kevin K.