Re: [PATCH, RFC] x86: make the GDT per-CPU

["Jan Beulich" <jbeulich@novell.com>]

>>> "Jan Beulich" <jbeulich@novell.com> 11.09.08 14:28 >>>
>>> Keir Fraser <keir.fraser@eu.citrix.com> 11.09.08 12:54 >>>
>>You would need to use l1e_write_atomic() in the context-switch code, to make
>>sure all VCPU's hypervisor reserved GDT mappings are always valid. Actually
>>you must at least use l1e_write() in any case -- it is not safe to not use
>>one of those macros on a live pagetable (by which I mean possibly in use by
>>some CPU) because a direct write of a PAE pte is not atomic and can cause
>>the pte to pass through a bogus intermediate state (which could be bogusly
>>prefetched by a CPU into its TLB. Yuk!).
>
>Ah, yes. l1e_write() should be sufficient, though, as the slot(s) that get(s)
>written cannot be validly in use on any CPU (for other than speculation).

Actually, not really - on PAE, any address ever put in these slots comes
from the Xen heap, so the upper bits are always clear. But for preventing
this to be a latent bug, I'll make the change anyway.

Btw., if there was a callout from the scheduler when a vCPU gets moved
to a new CPU, it would even be possible to get this out of the context
switch path altogether I think.

Jan