The stage of the pipeline occupied by any given domain can be stalled, which means that
the next incoming interrupt will not be delivered to the domain's handler, and will be
prevented from flowing down to the lowest priority domain(s) in the same move. While a
stage is stalled, pending interrupts accumulate in the domain's interrupt log, and
eventually get played when the stage is unstalled, by an internal operation called
synchronization.
When a domain has finished processing all the pending interrupts it has received, it then
calls a special Adeos service which yields the CPU to the next domain down the pipeline,
so the latter can process in turn the pending events it has been notified of, and this cycle
continues down to the lowest priority domain of the pipeline.
with inherent design, I would guess you mean the intel hardware design I suppose?IRQ sharing between deterministic and non-deterministic code (here: Xenomai and vanilla Linux) will never work, that's an inherent design issue, nothing Xenomai or ipipe-specific.
Jan