From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KkIXb-0001YH-Ok for qemu-devel@nongnu.org; Mon, 29 Sep 2008 09:11:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KkIXa-0001Xy-7A for qemu-devel@nongnu.org; Mon, 29 Sep 2008 09:11:55 -0400 Received: from [199.232.76.173] (port=45688 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KkIXZ-0001Xv-WF for qemu-devel@nongnu.org; Mon, 29 Sep 2008 09:11:54 -0400 Received: from mx2.suse.de ([195.135.220.15]:50551) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KkIXZ-00068p-6Z for qemu-devel@nongnu.org; Mon, 29 Sep 2008 09:11:54 -0400 Message-ID: <48E0D40D.3030102@suse.de> Date: Mon, 29 Sep 2008 15:11:41 +0200 From: Alexander Graf MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050408000504070203050706" Subject: [Qemu-devel] [PATCH] Clean up x86 CPUID definitions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: paul@codesourcery.com This is a multi-part message in MIME format. --------------050408000504070203050706 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit My core2duo patch introduced a vague statement of "missing features" in the CPUID specification. This patch addresses this by specifying exactly what is missing. While going along the missing CPUID entries I also stumbled across invalid and missing CPUID #defines while comparing them to the Intel Documentation. This patch also addresses these. I found them too minor to split them up in a separate patch. Furthermore I looked through CPUID functions > 5 and realized that it should be safe to bump the level to 10. I tried booting Linux with that and it worked fine. Signed-off-by: Alexander Graf --------------050408000504070203050706 Content-Type: text/x-patch; name="cpuid-cleanup.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="cpuid-cleanup.patch" Index: target-i386/helper.c =================================================================== --- target-i386/helper.c (revision 5349) +++ target-i386/helper.c (working copy) @@ -167,19 +167,22 @@ }, { .name = "core2duo", - /* original is on level 10 */ - .level = 5, + .level = 10, .family = 6, .model = 15, .stepping = 11, - /* the original CPU does have many more features that are - * not implemented yet */ + /* The original CPU also implements these features: + CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT, + CPUID_TM, CPUID_PBE */ .features = PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, + /* The original CPU also implements these ext features: + CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST, + CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3, - .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | - CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */ .xlevel = 0x8000000A, .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", }, @@ -240,7 +243,7 @@ .family = 6, .model = 2, .stepping = 3, - .features = PPRO_FEATURES | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, + .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, .xlevel = 0x80000008, /* XXX: put another string ? */ Index: target-i386/cpu.h =================================================================== --- target-i386/cpu.h (revision 5349) +++ target-i386/cpu.h (working copy) @@ -298,6 +298,7 @@ #define CPUID_PBE (1 << 31) #define CPUID_EXT_SSE3 (1 << 0) +#define CPUID_EXT_DTES64 (1 << 2) #define CPUID_EXT_MONITOR (1 << 3) #define CPUID_EXT_DSCPL (1 << 4) #define CPUID_EXT_VMX (1 << 5) @@ -308,8 +309,15 @@ #define CPUID_EXT_CID (1 << 10) #define CPUID_EXT_CX16 (1 << 13) #define CPUID_EXT_XTPR (1 << 14) -#define CPUID_EXT_DCA (1 << 17) -#define CPUID_EXT_POPCNT (1 << 22) +#define CPUID_EXT_PDCM (1 << 15) +#define CPUID_EXT_DCA (1 << 18) +#define CPUID_EXT_SSE41 (1 << 19) +#define CPUID_EXT_SSE42 (1 << 20) +#define CPUID_EXT_X2APIC (1 << 21) +#define CPUID_EXT_MOVBE (1 << 22) +#define CPUID_EXT_POPCNT (1 << 23) +#define CPUID_EXT_XSAVE (1 << 26) +#define CPUID_EXT_OSXSAVE (1 << 27) #define CPUID_EXT2_SYSCALL (1 << 11) #define CPUID_EXT2_MP (1 << 19) Index: target-i386/op_helper.c =================================================================== --- target-i386/op_helper.c (revision 5349) +++ target-i386/op_helper.c (working copy) @@ -1956,6 +1956,27 @@ ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; EDX = 0; break; + case 6: + /* Thermal and Power Leaf */ + EAX = 0; + EBX = 0; + ECX = 0; + EDX = 0; + break; + case 9: + /* Direct Cache Access Information Leaf */ + EAX = 0; /* Bits 0-31 in DCA_CAP MSR */ + EBX = 0; + ECX = 0; + EDX = 0; + break; + case 0xA: + /* Architectural Performance Monitoring Leaf */ + EAX = 0; + EBX = 0; + ECX = 0; + EDX = 0; + break; case 0x80000000: EAX = env->cpuid_xlevel; EBX = env->cpuid_vendor1; --------------050408000504070203050706--