From: Jon Loeliger <jdl@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/6] Make DDR interleaving mode work correctly
Date: Tue, 07 Oct 2008 17:26:28 -0500 [thread overview]
Message-ID: <48EBE214.5090200@freescale.com> (raw)
In-Reply-To: <2acbd3e40810071438k6108c8bg6a4202994a613115@mail.gmail.com>
Andy Fleming wrote:
> If Kim and Jon approve, I'll pull these 6 patches into my 85xx-next branch.
>
> On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
> <Haiying.Wang@freescale.com> wrote:
>> Fix some bugs:
>> 1. Correctly set intlv_ctl in cs_config.
>> 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
>> 3. Set base_address and total memory for each ddr controller in memory
>> controller interleaving mode.
>>
>> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Sounds good by me.
ACK.
jdl
next prev parent reply other threads:[~2008-10-07 22:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-03 16:36 [U-Boot] [PATCH 1/6] Make DDR interleaving mode work correctly Haiying Wang
2008-10-07 21:38 ` Andy Fleming
2008-10-07 22:26 ` Jon Loeliger [this message]
2008-10-08 5:39 ` Kumar Gala
2008-10-08 22:52 ` Kim Phillips
2008-10-13 18:20 ` Andy Fleming
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