From: Andi Kleen <andi@firstfloor.org>
To: Nick Piggin <nickpiggin@yahoo.com.au>
Cc: Dave Jones <davej@redhat.com>,
x86@kernel.org, Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: Update cacheline size on X86_GENERIC
Date: Fri, 10 Oct 2008 12:22:24 +0200 [thread overview]
Message-ID: <48EF2CE0.3080109@firstfloor.org> (raw)
In-Reply-To: <200810101945.32111.nickpiggin@yahoo.com.au>
Nick Piggin wrote:
>
>>> Anyway, GENERIC kernel should run well on all architectures, and while
>>> going too big causes slightly increased structures sometimes, going too
>>> small could result in horrible bouncing.
>> Exactly.
>>
>> That is it costs one percent or so on TPC, but I think the fix
>> for that is just to analyze where the problem is and size those
>> data structures based on the runtime cache size. Some subsystems
>> like slab do this already.
>
> Costs 1% on TPC? Is that 128 byte aligning data structures on
> Core2, or 64 byte aligning them on P4 that costs the performance?
The first. BTW it was a rough number from memory, in that ballpark.
Also the experiment was on older kernels, might be different now.
The second would undoubtedly be much worse.
-Andi
next prev parent reply other threads:[~2008-10-10 10:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-09 17:14 Update cacheline size on X86_GENERIC Dave Jones
2008-10-10 3:28 ` Nick Piggin
2008-10-10 7:46 ` Andi Kleen
2008-10-10 8:45 ` Nick Piggin
2008-10-10 10:22 ` Andi Kleen [this message]
2008-10-11 3:59 ` Nick Piggin
2008-10-11 8:08 ` Andi Kleen
2008-10-11 8:29 ` Nick Piggin
2008-10-11 11:22 ` Andi Kleen
2008-10-11 11:27 ` Rafael J. Wysocki
2008-10-11 11:42 ` Nick Piggin
2008-10-11 13:11 ` Andi Kleen
2008-10-11 13:48 ` Nick Piggin
2008-10-11 14:01 ` Andi Kleen
2008-10-12 5:56 ` Nick Piggin
2008-10-10 18:26 ` H. Peter Anvin
2008-10-11 3:56 ` Nick Piggin
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