[U-Boot] [PATCH v4] Add support for KMC KZM-ARM11-01 board

[Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>]

Hi,

This patch adds support for KMC KZM-ARM11-01.
It was rebased to "next" branch.

Regards,
Tomohiro

Signed-off-by: Atsuo Igarashi <atsuo_igarashi@tripeaks.co.jp>
Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>
----
Add support for KMC KZM-ARM11-01 board.

 MAKEALL                            |    1 +
 Makefile                           |    3 +
 board/kzm_arm11_01/Makefile        |   49 +++++++
 board/kzm_arm11_01/config.mk       |    1 +
 board/kzm_arm11_01/kzm_arm11_01.c  |   84 +++++++++++
 board/kzm_arm11_01/lowlevel_init.S |  281 ++++++++++++++++++++++++++++++++++++
 board/kzm_arm11_01/u-boot.lds      |   72 +++++++++
 include/configs/kzm_arm11_01.h     |  184 +++++++++++++++++++++++
 8 files changed, 675 insertions(+), 0 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index 9ccb9ac..22f65ed 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -522,6 +522,7 @@ LIST_ARM11="		\
 	apollon		\
 	imx31_litekit	\
 	imx31_phycore	\
+	kzm_arm11_01	\
 	mx31ads		\
 	smdk6400	\
 "
diff --git a/Makefile b/Makefile
index 017e4db..f334c57 100644
--- a/Makefile
+++ b/Makefile
@@ -2805,6 +2805,9 @@ imx31_litekit_config	: unconfig
 imx31_phycore_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31

+kzm_arm11_01_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 kzm_arm11_01 NULL mx31
+
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31

diff --git a/board/kzm_arm11_01/Makefile b/board/kzm_arm11_01/Makefile
new file mode 100644
index 0000000..7e2f8ca
--- /dev/null
+++ b/board/kzm_arm11_01/Makefile
@@ -0,0 +1,49 @@
+#
+# Derived from mx31ads
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= kzm_arm11_01.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/kzm_arm11_01/config.mk b/board/kzm_arm11_01/config.mk
new file mode 100644
index 0000000..d34dc02
--- /dev/null
+++ b/board/kzm_arm11_01/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x87f00000
diff --git a/board/kzm_arm11_01/kzm_arm11_01.c b/board/kzm_arm11_01/kzm_arm11_01.c
new file mode 100644
index 0000000..ed253d7
--- /dev/null
+++ b/board/kzm_arm11_01/kzm_arm11_01.c
@@ -0,0 +1,84 @@
+/*
+ * Derived from mx31ads
+ *
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init (void)
+{
+	int i;
+
+	/* CS0 & CS1: Nor Flash */
+	/*
+	 * CS0L, CS0A and CS0U values are from the RedBoot sources.
+	 */
+	__REG(CSCR_U(0)) = 0x00001801;
+	__REG(CSCR_L(0)) = 0x45450D01;
+	__REG(CSCR_A(0)) = 0x00450000;
+
+	__REG(CSCR_U(1)) = 0x00001801;
+	__REG(CSCR_L(1)) = 0x45450D01;
+	__REG(CSCR_A(1)) = 0x00450000;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+	gd->bd->bi_arch_number = MACH_TYPE_KZM_ARM11_01;/* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf("Board: KZM-ARM11-01\n");
+	return 0;
+}
diff --git a/board/kzm_arm11_01/lowlevel_init.S b/board/kzm_arm11_01/lowlevel_init.S
new file mode 100644
index 0000000..f2032a5
--- /dev/null
+++ b/board/kzm_arm11_01/lowlevel_init.S
@@ -0,0 +1,281 @@
+/*
+ * Derived from mx31ads
+ *
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]		/* for S0 */
+	str r1, [r0, #0x100]		/* for S1 */
+	str r1, [r0, #0x200]		/* for S2 */
+	str r1, [r0, #0x300]		/* for S3 */
+	str r1, [r0, #0x400]		/* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]		/* for S0 */
+	str r1, [r0, #0x110]		/* for S1 */
+	str r1, [r0, #0x210]		/* for S2 */
+	str r1, [r0, #0x310]		/* for S3 */
+	str r1, [r0, #0x410]		/* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]		/* for M0 */
+	str r1, [r0, #0x900]		/* for M1 */
+	str r1, [r0, #0xA00]		/* for M2 */
+	str r1, [r0, #0xB00]		/* for M3 */
+	str r1, [r0, #0xC00]		/* for M4 */
+	str r1, [r0, #0xD00]		/* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+	ldr r0, =WEIM_BASE
+	ldr r1, =0x00001003
+	str r1, [r0, #0x40]
+	ldr r1, =0x74741B01
+	str r1, [r0, #0x44]
+	ldr r1, =0x00740000
+	str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+/* LAN on CS5 setup */
+.macro init_cs5
+	ldr r0, =WEIM_BASE
+	ldr r1, =0x00001403
+	str r1, [r0, #0x50]
+	ldr r1, =0x44340D01
+	str r1, [r0, #0x54]
+	ldr r1, =0x00340000
+	str r1, [r0, #0x58]
+.endm /* init_cs5 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Redboot initializes very early AIPS, what for?
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF */
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015		/* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_cs4
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	REG	IPU_CONF, IPU_CONF_DI_EN	/* Switch on Display Interface */
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5		/* Use CKIH, MCU PLL off */
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS	/* Switch to MCU PLL */
+
+	/* 532-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF872660
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldreq	r1, MPCTL_PARAM_532
+	ldrne	r1, MPCTL_PARAM_532_27
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	ldreq	r1, UPCTL_PARAM_240
+	ldrne	r1, UPCTL_PARAM_240_27
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x000002C0
+	add	r1, r1, #0x00000006
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x0079d72a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x81000020, 0x00
+	REG8	0x80000033, 0xda
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	init_cs5
+
+	mov	pc, lr
+
+MPCTL_PARAM_532:
+	.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+	.word (((1-1) << 26) + ((15-1) << 16) + (9  << 10) + (13 << 0))
+UPCTL_PARAM_240:
+	.word (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
+UPCTL_PARAM_240_27:
+	.word (((2-1) << 26) + ((9 -1) << 16) + (8  << 10) + (8  << 0))
diff --git a/board/kzm_arm11_01/u-boot.lds b/board/kzm_arm11_01/u-boot.lds
new file mode 100644
index 0000000..aa87fcb
--- /dev/null
+++ b/board/kzm_arm11_01/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * Derived from mx31ads
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		/* WARNING - the following is hand-optimized to fit within */
+		/* the sector layout of our flash chips! XXX FIXME XXX */
+
+		cpu/arm1136/start.o			(.text)
+		board/kzm_arm11_01/libkzm_arm11_01.a	(.text)
+		lib_arm/libarm.a			(.text)
+		net/libnet.a				(.text)
+		drivers/mtd/libmtd.a			(.text)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+		common/env_embedded.o(.text)
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/include/configs/kzm_arm11_01.h b/include/configs/kzm_arm11_01.h
new file mode 100644
index 0000000..72f7b5a
--- /dev/null
+++ b/include/configs/kzm_arm11_01.h
@@ -0,0 +1,184 @@
+/*
+ * Derived from mx31ads
+ *
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the KMC KZM-ARM11-01 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
+#define CONFIG_MX31		1		/* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32	32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART	1
+#define CONFIG_SYS_MX31_UART1	1
+
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MXC_SPI		1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_FLASH
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot_addr=0xa0000000\0"					\
+	"uboot=kzm-arm11/u-boot.bin\0"					\
+	"kernel=kzm-arm11/uImage\0"					\
+	"nfsroot=${serverip}:${rootpath}\0"				\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "	\
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off ${uboot_addr} 0xa007ffff; "		\
+		"erase ${uboot_addr} 0xa007ffff; "			\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
+		"setenv filesize; saveenv\0"
+
+#define CONFIG_DRIVER_SMC911X		1
+#define CONFIG_DRIVER_SMC911X_BASE	0xb6020300
+#define CONFIG_DRIVER_SMC911X_32_BIT	1
+
+/*
+ * The KZM-ARM11-01 board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the SMC9118
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs a few hundred milliseconds wait for that after the
+ * initialization. Which means, at startup, you will not receive answers
+ * during the first few hundred milliseconds, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0		/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING		1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512		/* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/* S29GL512N NOR flash has 512 128KiB big sectors.	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI			1 /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER			1 /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION		1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV	"nor0"
+
+#endif /* __CONFIG_H */