Re: [PATCH v2] tcg/riscv64: Set vtype before whole-register vector moves

[Richard Henderson <richard.henderson@linaro.org>]

On 9/17/26 03:37, Max Chou wrote:
> According to the RISC-V unpriviledge spec,
>    "vset{i}vl{i} and whole register loads and stores do not depend upon
>     vtype."
> The whole-register vector move instructions reuqire legal vtype that
> trap when VILL is set.
> 
> The tcg_out_mov in tcg/riscv64 missed the vtype setup before emitting the
> OPC_VMVNR_V.
> 
> Fixes: d4be6ee1111 ("tcg/riscv: Implement vector mov/dup{m/i}")
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   tcg/riscv64/tcg-target.c.inc | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc
> index 2ce9d47a633..e3cfedb579d 100644
> --- a/tcg/riscv64/tcg-target.c.inc
> +++ b/tcg/riscv64/tcg-target.c.inc
> @@ -778,6 +778,10 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>           {
>               int lmul = type - riscv_lg2_vlenb;
>               int nf = 1 << MAX(lmul, 0);
> +
> +            if (s->riscv_cur_type == TCG_TYPE_COUNT) {
> +                set_vtype_len(s, type);
> +            }
>               tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1);
>           }
>           break;

Do you have a reproducer for this?  I ask because I still wonder how 
this can occur.

Given that

(1) all vector registers are call-clobbered, there should be none live 
across tcg_out_call_int (which clears the remembered vtype),

(2) the first vector action with no vector registers live must be a load 
or movi (which will initialize vtype).

Performing a move between vector registers when all such registers must 
be dead is... wrong.  It indicates that there's a bug elsewhere.

I'll throw an assert in here locally and see what happens...


r~