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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id eo9-20020a05600c82c900b003f0ad8d1c69sm10025559wmb.25.2023.04.24.13.11.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Apr 2023 13:11:12 -0700 (PDT) Message-ID: <48ea7b8f-8bc3-def5-3bfa-e4a1ee41971a@redhat.com> Date: Mon, 24 Apr 2023 22:11:11 +0200 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Reply-To: eric.auger@redhat.com Subject: Re: [kvm-unit-tests PATCH 3/6] arm: pmu: Add extra DSB barriers in the mem_access loop To: Alexandru Elisei Cc: eric.auger.pro@gmail.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com References: <20230315110725.1215523-1-eric.auger@redhat.com> <20230315110725.1215523-4-eric.auger@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Alexandru, On 4/21/23 12:25, Alexandru Elisei wrote: > Hi, > > On Wed, Mar 15, 2023 at 12:07:22PM +0100, Eric Auger wrote: >> The mem access loop currently features ISB barriers only. However >> the mem_access loop counts the number of accesses to memory. ISB >> do not garantee the PE cannot reorder memory access. Let's >> add a DSB ISH before the write to PMCR_EL0 that enables the PMU >> and after the last iteration, before disabling the PMU. >> >> Signed-off-by: Eric Auger >> Suggested-by: Alexandru Elisei >> >> --- >> >> This was discussed in https://lore.kernel.org/all/YzxmHpV2rpfaUdWi@monolith.localdoman/ >> --- >> arm/pmu.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arm/pmu.c b/arm/pmu.c >> index b88366a8..dde399e2 100644 >> --- a/arm/pmu.c >> +++ b/arm/pmu.c >> @@ -301,6 +301,7 @@ static void mem_access_loop(void *addr, long loop, uint32_t pmcr) >> { >> uint64_t pmcr64 = pmcr; >> asm volatile( >> + " dsb ish\n" > I think it might still be possible to reorder memory accesses which are > part of the loop after the DSB above and before the PMU is enabled below. > But the DSB above is needed to make sure previous memory accesses, which > shouldn't be counted as part of the loop, are completed. > > I would put another DSB after the ISB which enables the PMU, that way all > memory accesses are neatly sandwitches between two DSBs. > > Having 3 DSBs might look like overdoing it, but I reason it to be correct. > What do you think? I need more time to investigate this. I will come back to you next week as I am OoO this week. Sorry for the inconvenience. Thank you for the review! Eric > > Thanks, > Alex > >> " msr pmcr_el0, %[pmcr]\n" >> " isb\n" >> " mov x10, %[loop]\n" >> @@ -308,6 +309,7 @@ asm volatile( >> " ldr x9, [%[addr]]\n" >> " cmp x10, #0x0\n" >> " b.gt 1b\n" >> + " dsb ish\n" >> " msr pmcr_el0, xzr\n" >> " isb\n" >> : >> -- >> 2.38.1 >> >>