From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KsvCz-0002OD-5M for qemu-devel@nongnu.org; Thu, 23 Oct 2008 04:06:17 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KsvCw-0002O1-Og for qemu-devel@nongnu.org; Thu, 23 Oct 2008 04:06:16 -0400 Received: from [199.232.76.173] (port=45922 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KsvCw-0002Ny-Gs for qemu-devel@nongnu.org; Thu, 23 Oct 2008 04:06:14 -0400 Received: from mx20.gnu.org ([199.232.41.8]:20333) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KsvCv-00036e-Sp for qemu-devel@nongnu.org; Thu, 23 Oct 2008 04:06:14 -0400 Received: from lizzard.sbs.de ([194.138.37.39]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KsvCt-0000np-Bw for qemu-devel@nongnu.org; Thu, 23 Oct 2008 04:06:11 -0400 Received: from mail2.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m9N865hR020875 for ; Thu, 23 Oct 2008 10:06:05 +0200 Received: from [139.25.109.167] (mchn012c.mchp.siemens.de [139.25.109.167] (may be forged)) by mail2.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m9N864jf012311 for ; Thu, 23 Oct 2008 10:06:05 +0200 Message-ID: <4900306C.2060104@siemens.com> Date: Thu, 23 Oct 2008 10:06:04 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <48FC78C2.3010707@siemens.com> In-Reply-To: <48FC78C2.3010707@siemens.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [PATCH] x86: Fix conditions for Virtual Wire IRQ delivery Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Jan Kiszka wrote: > QEMU is implementing the Virtual Wire mode to attach the PIC to modern, > APIC-supporting CPUs. But Intel's MP spec says that PIC interrupts then > flow through the APICs, thus they also have to be enabled. Patch below > fixes the test logic accordingly, avoiding delivery in case an APIC is > disabled. > > Signed-off-by: Jan Kiszka > --- > hw/apic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > Index: b/hw/apic.c > =================================================================== > --- a/hw/apic.c > +++ b/hw/apic.c > @@ -526,7 +526,7 @@ int apic_accept_pic_intr(CPUState *env) > > lvt0 = s->lvt[APIC_LVT_LINT0]; > > - if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || > + if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && > (lvt0 & APIC_LVT_MASKED) == 0) > return 1; > This patch turned out to be incorrect (SDM 3A, 5.3.1), please ignore it. Jan -- Siemens AG, Corporate Technology, CT SE 2 Corporate Competence Center Embedded Linux