From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Hawkins Date: Thu, 20 Nov 2008 10:04:39 -0800 Subject: [U-Boot] Problems booting without BDI In-Reply-To: <4925A3A3.7080203@gmail.com> References: <492597D4.5030804@ovro.caltech.edu> <4925A3A3.7080203@gmail.com> Message-ID: <4925A6B7.6030702@ovro.caltech.edu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Alemao, Ben's comment is in addition to my comment: >> The assignments for the 8349 are: >> >> CFG_RS[0:2] = LGPL[0, 1, 3] >> CFG_CLKIN_DIV = LGPL[5] >> These need to be setup to tell the processor to load from local bus flash, and then ... > To somewhat re-phrase what Dave mentioned, one common issue is that at > boot time, the four least-significant local bus address bits are driven > by different signals than the standard local bus address bits (sorry, > don't have the documentation here so don't know the exact names). > Without this you can't red the RCW words from NOR flash. Compare your > schematic to the one for the MPC8349EMDS to make sure you got this right. During the boot sequence from local bus flash, the LA[27:31] lines carry the boot addresses, and the lower-addresses cycle without pulsing the LALE (local bus address latch enable) signal, so if your schematic drives the flash address lines with *latched* versions of LA[27:31] then you're also in trouble. Hopefully thats not your problem though ... Cheers, Dave