From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LEDVx-0007jR-4H for qemu-devel@nongnu.org; Sat, 20 Dec 2008 20:53:53 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LEDVv-0007jF-0W for qemu-devel@nongnu.org; Sat, 20 Dec 2008 20:53:51 -0500 Received: from [199.232.76.173] (port=53871 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LEDVu-0007jC-T5 for qemu-devel@nongnu.org; Sat, 20 Dec 2008 20:53:50 -0500 Received: from pop-siberian.atl.sa.earthlink.net ([207.69.195.71]:45710) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LEDVu-0007v5-5w for qemu-devel@nongnu.org; Sat, 20 Dec 2008 20:53:50 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=[192.168.0.90]) by pop-siberian.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1LEDVq-0001Es-00 for qemu-devel@nongnu.org; Sat, 20 Dec 2008 20:53:46 -0500 Message-ID: <494DA1A8.1060106@earthlink.net> Date: Sat, 20 Dec 2008 20:53:44 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060100020505040209080809" Subject: [Qemu-devel] [PATCH] add Arbiter Enable Register support to sparc iommu Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------060100020505040209080809 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Add Arbiter Enable Register support to sparc iommu for MBus based systems. --------------060100020505040209080809 Content-Type: text/plain; name="iommu.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="iommu.diff.txt" --- hw/iommu.c (revision 6110) +++ hw/iommu.c (working copy) @@ -78,6 +78,19 @@ #define IOMMU_AFAR (0x1004 >> 2) +#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ +#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ +#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ +#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ +#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ +#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ +#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ +#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ +#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ +#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ +#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ +#define IOMMU_AER_MASK 0x801f000f + #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ @@ -196,6 +209,9 @@ s->regs[saddr] = val; qemu_irq_lower(s->irq); break; + case IOMMU_AER: + s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; + break; case IOMMU_AFSR: s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; qemu_irq_lower(s->irq); @@ -344,6 +360,7 @@ s->regs[IOMMU_CTRL] = s->version; s->regs[IOMMU_ARBEN] = IOMMU_MID; s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; + s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; qemu_irq_lower(s->irq); } --------------060100020505040209080809--