From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Rhodes Subject: Re: ASoC: pxa2xx-i2s Date: Thu, 22 Jan 2009 11:03:42 -0600 Message-ID: <4978A6EE.4090107@acdstar.com> References: <4975E030.5080905@acdstar.com> <4975F160.8040001@gmail.com> <4976042B.6060604@acdstar.com> <49764F15.6080008@acdstar.com> <20090121132313.GA29953@sirena.org.uk> <49775159.7070708@linespeed.net> <20090121193230.GA15911@sirena.org.uk> <497781D8.50003@acdstar.com> <20090121222718.GA23539@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from manowar.linespeed.net (linespeed.net [75.146.159.141]) by alsa0.perex.cz (Postfix) with ESMTP id CE0D51038D2 for ; Thu, 22 Jan 2009 18:03:53 +0100 (CET) In-Reply-To: <20090121222718.GA23539@sirena.org.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Mark Brown Cc: alsa-devel@alsa-project.org List-Id: alsa-devel@alsa-project.org Mark Brown wrote: > On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote: > > >> No, the 270 is the clock master on the I2S bus. The codec is sourcing >> the clock input using the PLL. I apologize for being unclear. >> > > I think it's me that's not being clear, sorry - I'm trying to find out > is if the LRCLK and BCLK signals on the I2S bus itself are being driven > by the codec or by the I2S controller. If the codec driver is the clock > master then your earlier speculation that your problems with the I2S > controller may be due to some interaction with the codec driver are more > likely to be true. LCRK and BCLK are configured as inputs. The Codec is not the bus master.