From: Philippe Gerum <rpm@xenomai.org>
To: federico.ridolfo@domain.hid
Cc: xenomai@xenomai.org
Subject: Re: [Xenomai-help] PowerPC irq unmask
Date: Fri, 23 Jan 2009 19:07:06 +0100 [thread overview]
Message-ID: <497A074A.1050104@domain.hid> (raw)
In-Reply-To: <4979F92A.70702@domain.hid>
Federico Ridolfo wrote:
> Ok, i'm debugging the problem, but i have not a solution.
> I compiled the kernel with the debug switch for irq.c.
> In addition i added the mpc52xx_psc_spi module in my
> .config.
> So, now i'm sure that the irq used in mpc52xx_psc_spi
> for the PSC3 is 131 and for PSC6 is 132:
>
> # dmesg
> mpc52xx-psc-spi f0002400.spi: probe called without platform data, no
> (de)activate_cs function will be called
> irq: irq_create_mapping(0xc041d2a0, 0x84)
> irq: -> using host @c041d2a0
> irq: -> obtained virq 132
>
Please send all the IRQ related information, you get in the boot log, because
the few lines above do not match what your dts file below says.
As far as I understand those lines, the generic IRQ code is asked to create a
virtual mapping for hwirq 132 out of the OF specs, and this hint is kept so that
you actually get virq 132. So far so good.
However, to get asked for 132, your dts file should have specified an intspec
which rather looks like { 2 4 <sense-type> } and not { 2 3 <sense-type> } as
mentioned in the spi@domain.hid block. { 2 3 <sense-type> } for PSC3 in SPI mode would
rather give us hwirq 131 (the hairy computation determining the hwirq number
from the inspec is available from mpc52xx_irqhost_xlate()).
So either you are not booting with the blob that matches the dts file below, or
the console output above is misleading. In short, I'm lost.
> I'm using the same irqs for my rtdm spi driver, but it doesnìt work.
> If i reboot the board and try my rtdm driver, the result is -ENODEV
>
> If i "modprobe mpc52xx_psc_spi" and retry my rtdm driver -> the board
> hangs for ever.
> I have the same result also if i "rrmod mpc52xx_psc_spi" before.
> My dts is:
> /dts-v1/;
>
> / {
> model = "colgp,cirneco5200";
> compatible = "colgp,cirneco5200";
> #address-cells = <1>;
> #size-cells = <1>;
>
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> PowerPC,5200@domain.hid {
> device_type = "cpu";
> reg = <0>;
> d-cache-line-size = <32>;
> i-cache-line-size = <32>;
> d-cache-size = <0x4000>; // L1, 16K
> i-cache-size = <0x4000>; // L1, 16K
> timebase-frequency = <0>; // from bootloader
> bus-frequency = <0>; // from bootloader
> clock-frequency = <0>; // from bootloader
> };
> };
>
> memory {
> device_type = "memory";
> reg = <0x00000000 0x04000000>; // 64MB
> //reg = <0x00000000 0x08000000>; // 64MB
> //reg = <0x00000000 0x10000000>; // 256MB
> };
>
> soc5200@domain.hid {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "fsl,mpc5200b-immr";
> ranges = <0 0xf0000000 0x0000c000>;
> reg = <0xf0000000 0x00000100>;
> bus-frequency = <0>; // from bootloader
> system-frequency = <0>; // from bootloader
>
> cdm@domain.hid {
> compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> reg = <0x200 0x38>;
> };
>
> mpc5200_pic: interrupt-controller@domain.hid {
> // 5200 interrupts are encoded into two levels;
> interrupt-controller;
> #interrupt-cells = <3>;
> device_type = "interrupt-controller";
> compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> reg = <0x500 0x80>;
> };
>
> // General Purpose Timer
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <0>;
> reg = <0x600 0x10>;
> interrupts = <1 9 0>;
> interrupt-parent = <&mpc5200_pic>;
> fsl,has-wdt;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <1>;
> reg = <0x610 0x10>;
> interrupts = <1 10 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <2>;
> reg = <0x620 0x10>;
> interrupts = <1 11 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <3>;
> reg = <0x630 0x10>;
> interrupts = <1 12 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <4>;
> reg = <0x640 0x10>;
> interrupts = <1 13 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <5>;
> reg = <0x650 0x10>;
> interrupts = <1 14 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <6>;
> reg = <0x660 0x10>;
> interrupts = <1 15 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> timer@domain.hid {
> compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> cell-index = <7>;
> reg = <0x670 0x10>;
> interrupts = <1 16 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> rtc@domain.hid { // Real time clock
> compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> device_type = "rtc";
> reg = <0x800 0x100>;
> interrupts = <1 5 0 1 6 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> can@domain.hid {
> compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> cell-index = <0>;
> interrupts = <2 17 0>;
> interrupt-parent = <&mpc5200_pic>;
> reg = <0x900 0x80>;
> };
>
> can@domain.hid {
> compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> cell-index = <1>;
> interrupts = <2 18 0>;
> interrupt-parent = <&mpc5200_pic>;
> reg = <0x980 0x80>;
> };
>
> gpio@domain.hid {
> compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> reg = <0xb00 0x40>;
> interrupts = <1 7 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> gpio@domain.hid {
> compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> reg = <0xc00 0x40>;
> interrupts = <1 8 0 0 3 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> spi@domain.hid {
> compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> reg = <0xf00 0x20>;
> interrupts = <2 13 0 2 14 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> usb@domain.hid {
> compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> reg = <0x1000 0xff>;
> interrupts = <2 6 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> dma-controller@domain.hid {
> device_type = "dma-controller";
> compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> reg = <0x1200 0x80>;
> interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> 3 4 0 3 5 0 3 6 0 3 7 0
> 3 8 0 3 9 0 3 10 0 3 11 0
> 3 12 0 3 13 0 3 14 0 3 15 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> xlb@domain.hid {
> compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> reg = <0x1f00 0x100>;
> };
>
> serial@domain.hid { // PSC1
> device_type = "serial";
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> port-number = <0>; // Logical port assignment
> cell-index = <0>;
> reg = <0x2000 0x100>;
> interrupts = <2 1 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> serial@domain.hid { // PSC2
> device_type = "serial";
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> cell-index = <1>;
> port-number = <1>;
> reg = <0x2200 0x100>;
> interrupts = <2 2 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
>
> spi@domain.hid { // PSC3 in spi mode
> compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
> cell-index = <2>;
> port-number = <2>;
> reg = <0x2400 0x100>;
> interrupts = <2 3 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> // PSC3 in CODEC mode example
> //i2s@domain.hid { // PSC3
> // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
> // cell-index = <2>;
> // reg = <0x2400 0x100>;
> // interrupts = <2 3 0>;
> // interrupt-parent = <&mpc5200_pic>;
> //};
>
> //serial@domain.hid { // PSC3
> // device_type = "serial";
> // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> // cell-index = <2>;
> // reg = <0x2400 0x100>;
> // interrupts = <2 3 0>;
> // interrupt-parent = <&mpc5200_pic>;
> //};
>
> serial@domain.hid { // PSC4 uart
> device_type = "serial";
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> cell-index = <3>;
> port-number = <3>;
> reg = <0x2600 0x100>;
> interrupts = <2 11 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> serial@domain.hid { // PSC5 uart
> device_type = "serial";
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> cell-index = <4>;
> port-number = <4>;
> reg = <0x2800 0x100>;
> interrupts = <2 12 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> // PSC6 in spi mode example
> spi@domain.hid { // PSC6
> compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
> cell-index = <5>;
> port-number = <5>;
> reg = <0x2c00 0x100>;
> interrupts = <2 4 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
>
> //serial@domain.hid { // PSC6 in UART mode
> // device_type = "serial";
> // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> // cell-index = <5>;
> // port-number = <5>;
> // reg = <0x2c00 0x100>;
> // interrupts = <2 4 0>;
> // interrupt-parent = <&mpc5200_pic>;
> //};
>
>
> ethernet@domain.hid {
> device_type = "network";
> compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> reg = <0x3000 0x400>;
> local-mac-address = [ 00 00 00 00 00 00 ];
> interrupts = <2 5 0>;
> interrupt-parent = <&mpc5200_pic>;
> phy-handle = <&phy0>;
> };
>
> mdio@domain.hid {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
> reg = <0x3000 0x400>; // fec range, since we need to
> setup fec interrupts
> interrupts = <2 5 0>; // these are for "mii command
> finished", not link changes & co.
> interrupt-parent = <&mpc5200_pic>;
>
> phy0: ethernet-phy@domain.hid {
> device_type = "ethernet-phy";
> reg = <0>;
> };
> };
>
> ata@domain.hid {
> device_type = "ata";
> compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> reg = <0x3a00 0x100>;
> interrupts = <2 7 0>;
> interrupt-parent = <&mpc5200_pic>;
> };
>
> i2c@domain.hid {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> cell-index = <0>;
> reg = <0x3d00 0x40>;
> interrupts = <2 15 0>;
> interrupt-parent = <&mpc5200_pic>;
> fsl5200-clocking;
> };
>
> i2c@domain.hid {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> cell-index = <1>;
> reg = <0x3d40 0x40>;
> interrupts = <2 16 0>;
> interrupt-parent = <&mpc5200_pic>;
> fsl5200-clocking;
> rtc@domain.hid {
> device_type = "rtc";
> compatible = "epson,pcf8563";
> reg = <0x51>;
> };
> };
> sram@domain.hid {
> compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
> reg = <0x8000 0x4000>;
> };
> };
>
> pci@domain.hid {
> #interrupt-cells = <1>;
> #size-cells = <2>;
> #address-cells = <3>;
> device_type = "pci";
> compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
> 0xc000 0 0 2 &mpc5200_pic 1 1 3
> 0xc000 0 0 3 &mpc5200_pic 1 2 3
> 0xc000 0 0 4 &mpc5200_pic 1 3 3
>
> 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
> 0xc800 0 0 2 &mpc5200_pic 1 2 3
> 0xc800 0 0 3 &mpc5200_pic 1 3 3
> 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
> clock-frequency = <0>; // From boot loader
> interrupts = <2 8 0 2 9 0 2 10 0>;
> interrupt-parent = <&mpc5200_pic>;
> bus-range = <0 0>;
> ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
> 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
> };
> };
>
> Ideas? Thanks for your help
>
> Philippe Gerum wrote:
>> Federico Ridolfo wrote:
>>
>>> Hi all,
>>> my platform is a mpc5200b based one. I wrote
>>> some rtdm driver for that platform on linux-2.6.18
>>> kernel. Some info:
>>> - ARCH=ppc
>>> - no fdt (so no dts)
>>> - u-boot
>>> - xenomai 2.3.2,
>>> - adeos-ipipe-2.6.18-ppc-1.5-01.patch
>>> All works fine.
>>>
>>> Now i want to use:
>>> - ARCH = powerpc
>>> - linux kernel from denx: ipipe-2.6-26-powerpc-2.4-03
>>> - fdt (so i have a dts file)
>>> - xenomai-2.4.6.1
>>> - u-boot
>>> Ok. My board boots, all peripheral s work. Xenomai works, but
>>> my rtdm drivers don't work. The problem is that the rtdm_irq_request
>>> returns -ENODEV coming from line 166 in wrappers.h:
>>> ...
>>> #else /* > 2.6.19 */
>>> #define rthal_irq_chip_enable(irq) \
>>> ({ \
>>> int __err__ = 0; \
>>> if (unlikely(rthal_irq_handlerp(irq)->unmask == NULL)) \
>>> __err__ = -ENODEV; \
>>> else \
>>> rthal_irq_handlerp(irq)->unmask(irq); \
>>> __err__; \
>>> })
>>> ...
>>> Seems that adeos doesn't not set the unmask function. In the linux kernel
>>> the right functions for my pic in in
>>> arch/powerpc/platforms/52xx/mpc52xx_pic.c
>>> I thing i have to add some code in mpc52xx_pic.c in order to match
>>> device tree table
>>>
>> To complete my previous answer: unless you have a very particular hw design, it
>> is unlikely that the PIC code is missing anything to support your board.
>>
>>
>>> and also something in my dts file.
>>>
>> However, a too generic device tree description may not reflect all the
>> peripherals you have on your board, so yes, updating it may be needed so that
>> the platform code maps the hw interrupt sources you want.
>>
>> I suspect you will have no regular drivers on these IRQs, so /proc/interrupts
>> should not list them.
>>
>> The point is: are those interrupts sources known from the kernel? Enabling the
>> debug switch in arch/powerpc/kernel/irq.c should give you some hints about which
>> hw IRQ sources are actually enumerated then mapped on your board (remember to
>> increase the console_loglevel or set ignore_loglevel to get this ouput). If you
>> don't find those you need, then you will likely want to fix the dts file.
>>
>> Any help is very usefull!!!
>>
>>> Thanks
>>>
>>>
>>> --
>>> chicco
>>>
>>> _______________________________________________
>>> Xenomai-help mailing list
>>> Xenomai-help@domain.hid
>>> https://mail.gna.org/listinfo/xenomai-help
>>>
>>>
>>
>>
>
>
>
--
Philippe.
next prev parent reply other threads:[~2009-01-23 18:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-01-23 7:32 [Xenomai-help] PowerPC irq unmask Federico Ridolfo
2009-01-23 8:52 ` Philippe Gerum
2009-01-23 9:10 ` Federico Ridolfo
2009-01-23 9:48 ` Philippe Gerum
2009-01-23 10:16 ` Federico Ridolfo
2009-01-23 10:25 ` Philippe Gerum
2009-01-23 17:06 ` Federico Ridolfo
2009-01-23 18:07 ` Philippe Gerum [this message]
2009-01-23 18:18 ` Federico Ridolfo
2009-01-24 9:58 ` Philippe Gerum
2009-01-26 11:35 ` Federico Ridolfo
2009-01-26 14:52 ` Bosko Radivojevic
2009-01-27 7:39 ` Federico Ridolfo
2009-01-23 19:29 ` Wolfgang Grandegger
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