[U-Boot] [PATCH 1/3] Add support for W90P710 ARM7 SoC

[Vovk Konstantin <vks@svitonline.com>]

Add support for CPU and serial communication.
Interrupt not used for work with Timer0.
Serial communication configured for UART0.
---
  cpu/arm720t/cpu.c                       |   48 ++++++-
  cpu/arm720t/interrupts.c                |   82 +++++++++++-
  cpu/arm720t/serial.c                    |  115 ++++++++++++++-
  cpu/arm720t/start.S                     |   30 ++++-
  include/asm-arm/arch-arm720t/W90P710.h  |  240 +++++++++++++++++++++++++++++++
  include/asm-arm/arch-arm720t/hardware.h |    2 +
  include/asm-arm/io.h                    |    4 +
  7 files changed, 512 insertions(+), 9 deletions(-)
  create mode 100644 include/asm-arm/arch-arm720t/W90P710.h

diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 5ac8f59..1cee570 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -73,7 +73,7 @@ int cleanup_before_linux (void)
  	/* go to high speed */
  	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
  #endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) || defined(CONFIG_W90P710)
  	disable_interrupts ();
  	/* Nothing more needed */
  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
@@ -253,6 +253,52 @@ int dcache_status (void)
  	{
  	}
  #elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
+
+#elif defined(CONFIG_W90P710)
+void icache_enable (void)
+{
+	PUT_REG (REG_CAHCON, 0x05);	/* Flush I-cache */
+	while (GET_REG (REG_CAHCON));	/* Wait for operation progress */
+
+	PUT_REG (REG_CAHCNF, 0x01);	/* Enable I-CACHE */
+}
+
+void icache_disable (void)
+{
+	PUT_REG (REG_CAHCON, 0x05);	/* Flush I-cache */
+	while (GET_REG (REG_CAHCON));	/* Wait for operation progress */
+	/* Disable I-cache */
+	PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) & (~0x01));
+}
+
+int icache_status (void)
+{
+	/* Check if I-Cache enable */
+	return (GET_REG (REG_CAHCNF) & 0x01) != 0;
+}
+
+void dcache_enable (void)
+{
+	PUT_REG (REG_CAHCON, 0x06);	/* Flush D-cache */
+	while (GET_REG (REG_CAHCON));	/* Wait for operation progress */
+
+	PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) | 0x02); /* Enable D-CACHE */
+}
+
+void dcache_disable (void)
+{
+	PUT_REG (REG_CAHCON, 0x06);	/* Flush D-cache */
+	while (GET_REG (REG_CAHCON));	/* Wait for operation progress  */
+	/* Disable D-cache */
+	PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) & (~0x02));
+}
+
+int dcache_status (void)
+{
+	/* Check if D-Cache enable */
+	return (GET_REG (REG_CAHCNF) & 0x02) != 0;
+}
+
  #else
  #error No icache/dcache enable/disable functions defined for this CPU type
  #endif
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 39ed345..050610a 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -50,6 +50,14 @@
  #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
  #endif

+#ifdef CONFIG_W90P710
+#undef  TIMER_LOAD_VAL
+/* We have the 24-bit timer - set maximum value*/
+#define TIMER_LOAD_VAL (0x00FFFFFF)
+#undef  READ_TIMER
+#define READ_TIMER (GET_REG(REG_TDR0) & 0xFFFFFF)
+#endif
+
  #ifdef CONFIG_S3C4510B
  /* require interrupts for the S3C4510B */
  # ifndef CONFIG_USE_IRQ
@@ -80,6 +88,8 @@ void do_irq (struct pt_regs *pt_regs)
      pfnct = (void (*)(void))VICVectAddr;

      (*pfnct)();
+#elif defined(CONFIG_W90P710)
+/* No do_irq() for W90P710 as yet */
  #else
  #error do_irq() not defined for this CPU type
  #endif
@@ -185,7 +195,18 @@ int interrupt_init (void)
  	PUT32(T0MCR, 0);
  	PUT32(T0TC, 0);
  	PUT32(T0TCR, 1);	/* enable timer0 */
-
+#elif defined(CONFIG_W90P710)
+	/* Stop Timer0 */
+	PUT_REG(REG_TCR0, 0x00000000);
+	/* Enable Timer clock */
+	PUT_REG(REG_CLKSEL, GET_REG(REG_CLKSEL) | 0x40);
+	/* Set Timer0 reload value*/
+	PUT_REG(REG_TICR0, (TIMER_LOAD_VAL));
+	/* Save to lastdec value that we load to the timer*/
+	lastdec = TIMER_LOAD_VAL;
+	/* CEN=1 - Timer0 Start counting, MODE = 01 - Timer0 is operat in pereodic mode  */
+	/* IE = 0 - Disable Timer0 interrupt Prescaler=0x0E Timer clock is 15000000/(14+1)=1Mhz*/
+	PUT_REG(REG_TCR0, 0x4800000E);
  #else
  #error No interrupt_init() defined for this CPU type
  #endif
@@ -305,6 +326,65 @@ void udelay (unsigned long usec)

  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
  	/* No timer routines for IntegratorAP/CM720T as yet */
+
+#elif defined(CONFIG_W90P710)
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	ulong timestamp_in_us;
+	/* Get timestamp in uS */
+	timestamp_in_us = get_timer_masked ();
+	/* Convert timestamp in mS and subtract base*/
+	return timestamp_in_us/1000 - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now){	/* normal mode */
+		timestamp += (lastdec - now);
+	}
+	else{			/* we have an overflow ... */
+		timestamp += (lastdec + TIMER_LOAD_VAL - now);
+	}
+	lastdec = now;
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime;
+	signed long diff;
+
+	endtime = get_timer_masked () + usec;
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked (usec);
+}
+
  #else
  #error Timer routines not defined for this CPU type
  #endif
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 54a9b31..e9bc652 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -169,13 +169,13 @@ int serial_init (void)

  void serial_putc (const char c)
  {
-	if (c == '\n')
-	{
-		while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
+	if (c == '\n') {
+		/* Wait for empty U0THR */
+		while((GET8(U0LSR) & (1<<5)) == 0);
  		PUT8(U0THR, '\r');
  	}
-
-	while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
+	/* Wait for empty U0THR */
+	while((GET8(U0LSR) & (1<<5)) == 0);
  	PUT8(U0THR, c);
  }

@@ -199,4 +199,109 @@ int serial_tstc (void)
  	return (GET8(U0LSR) & 1);
  }

+#elif defined(CONFIG_W90P710)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#include <asm/arch/hardware.h>
+
+void serial_setbrg (void)
+{
+	unsigned int divider = 0;
+
+	/* use values for 15Mhz quarts */
+	switch (gd->baudrate) {
+	case   1200:	divider = 779;	break;
+	case   2400:	divider = 389;	break;
+	case   4800:	divider = 193;	break;
+	case   9600:	divider =  96;	break;
+	case  14400:	divider =  65;	break;
+	case  19200:	divider =  47;	break;
+	case  38400:	divider =  22;	break;
+	case  57600:	divider =  14;	break;
+	case 115200:	divider =   6;	break;
+	default:	hang ();	break;
+	}
+
+	/* Reset LCR register and disable Uart interrupt*/
+	PUT_REG (REG_UART0_LCR, 0x0);
+	PUT_REG (REG_UART0_IER, 0x0);
+
+	/* Set baud rate to mentioned in divider */
+	/* Set DLAB to '1' to access Divisor */
+	PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) | (1 << 7));
+	PUT_REG (REG_UART0_LSB, (divider & 0xFF));
+	PUT_REG (REG_UART0_MSB, ((divider >> 8) & 0xFF));
+	/* Reset DLAB to '0' to access RBR, THR, IER */
+	PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) & (~(1 << 7)));
+
+	/* Set port parameters 8 bit, 1 stop, no parity  */
+	PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) |
+				((1 << 0) | (1 << 1)));
+
+	/*
+	 * Set the RX FIFO trigger level to 8 bytes,
+	 * reset RX, TX FIFO, Enable FIFO
+	 */
+	PUT_REG (REG_UART0_FCR, ((0x2 << 6) | (1 << 2) | (1 << 1) | (1 << 0)));
+
+	/* Reset timeout comparator */
+	PUT_REG (REG_UART0_TOR, 0x0);
+}
+
+/* Initialise the serial port with the given baudrate. Settings are 8N1 */
+int serial_init (void)
+{
+	unsigned int Temp;
+
+	serial_setbrg ();
+
+	/* Set GPIO_CFG to use pins PORT5_0 as TXD0  and PORT5_1 as RXD0 */
+	Temp = GET_REG (REG_GPIO_CFG5);
+	Temp |= 0X00000005;
+	Temp &= 0XFFFFFFF5;
+	PUT_REG (REG_GPIO_CFG5, Temp);
+	return (0);
+}
+
+/* Check for Transmitter holding register is empty */
+void CheckForUART0TXReady (void)
+{
+	unsigned int Status;
+
+	do {
+		Status = GET_REG (REG_UART0_LSR);
+	}
+	while (!(Status & (1 << 6)));	/* Check for TE=1*/
+}
+
+/*Put one character to Uart0 TX FIFO.  Add 'LF' after 'CR'*/
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		/* Wait for empty THR */
+		CheckForUART0TXReady ();
+		PUT_REG (REG_UART0_TX, '\r');
+	}
+	CheckForUART0TXReady ();
+	PUT_REG (REG_UART0_TX, c);
+}
+
+int serial_getc (void)
+{
+	while ((GET_REG (REG_UART0_LSR) & 1) == 0);
+	return GET_REG(REG_UART0_RX);
+}
+
+int serial_tstc (void)
+{
+	return (GET_REG (REG_UART0_LSR) & 1);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
  #endif
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S
index 022b873..055515a 100644
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -1,8 +1,8 @@
  /*
   *  armboot - Startup Code for ARM720 CPU-core
   *
- *  Copyright (c) 2001	Marius Gr?ger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Z?pke <azu@sysgo.de>
+ *  Copyright (c) 2001	Marius Gr???ger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Z???pke <azu@sysgo.de>
   *
   * See file CREDITS for list of people who contributed to this
   * project.
@@ -224,6 +224,14 @@ PLLSTAT_ADR:	.word	PLLSTAT
  VPBDIV_ADR:	.word	VPBDIV
  MEMMAP_ADR:	.word	MEMMAP

+#elif defined(CONFIG_W90P710)
+
+#define CAHCON		0xFFF02004	/* Cache control register */
+#define AIC_MDCR	0xFFF82124	/* AIC Mask Disable Control Register */
+#define CAHCNF		0xFFF02000	/* Cache configuration register */
+#define IDREG		0xFFF00000	/* W90P710 CHIP ID */
+#define CKSKEW		0xFFF01F00	/* Clock Skew Control register */
+
  #endif

  cpu_init_crit:
@@ -368,6 +376,21 @@ lock_loop:
  	ldr	r0, VPBDIV_ADR
  	mov	r1, #0x01	/* VPB clock is same as process clock */
  	str	r1, [r0]
+
+#elif defined(CONFIG_W90P710)
+	/* Disable Interrupt */
+	LDR	r0, =AIC_MDCR
+	LDR	r1, =0x7FFFE
+	STR	r1, [r0]
+	/* Disable FIQ and IRQ */
+	MRS	r0, CPSR
+	ORR	r0, r0, #0xC0
+	MSR	CPSR_c, r0
+	/* Disable I-Cache and D-cache entirely */
+	LDR	r1,=CAHCNF
+	MOV	r0, #0x0
+	STR	r0, [r1]
+	
  #else
  #error No cpu_init_crit() defined for current CPU type
  #endif
@@ -606,6 +629,9 @@ reset_cpu:
  .globl reset_cpu
  reset_cpu:
  	mov	pc, r0
+#elif defined(CONFIG_W90P710)
+/* Nothing done here as reseting the CPU is board specific, depending on external peripherals see lowlevel_init.c*/
+
  #else
  #error No reset_cpu() defined for current CPU type
  #endif
diff --git a/include/asm-arm/arch-arm720t/W90P710.h b/include/asm-arm/arch-arm720t/W90P710.h
new file mode 100644
index 0000000..c6be724
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/W90P710.h
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2008
+ * KSL Embedded Development Team <www.kslemb.com>
+ * Konstantin Vovk <ksl@kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:   Nuvoton W90P710 register layout definition
+ */
+#ifndef _W90P710_H
+#define _W90P710_H
+
+/* L1 8KB on chip SRAM base address */
+#define SRAM_BASE       0xFFE00000
+
+#define GET_REG(reg)       (*((volatile unsigned int *)(reg)))
+#define PUT_REG(reg, val)  (*((volatile unsigned int *)(reg))) = (unsigned int)(val)
+
+/* System Address Map - Defines the register base address */
+#define	GCR_BA		0xFFF00000	/* Global Control */
+#define	EBI_BA		0xFFF01000	/* EBI Control */
+#define	CACHE_BA	0xFFF02000	/* Cache Control */
+#define	EMC_BA		0xFFF03000	/* Ethernet MAC */
+#define	GDMA_BA		0xFFF04000	/* GDMA control */
+#define	USBH_BA		0xFFF05000	/* USB Host Control */
+#define	USBD_BA		0xFFF06000	/* USB Device Control */
+#define	FMI_BA		0xFFF07000	/* Flash Memory Card Interface */
+#define	LCD_BA		0xFFF08000	/* Display, LCM Interface & Bypass */
+#define	ADO_BA		0xFFF09000	/* Audio Control */
+
+#define	UART0_BA	0xFFF80000	/* UART0 Control (console) */
+#define	UART1_BA	0xFFF80100	/* UART1 Control (Bluetooth) */
+#define	UART2_BA	0xFFF80200	/* UART2 Control (IrDA) */
+#define	UART3_BA	0xFFF80300	/* UART3 Control (micro-printer) */
+#define	TMR_BA		0xFFF81000	/* Timer */
+#define	AIC_BA		0xFFF82000	/* Interrupt Controller */
+#define	GPIO_BA		0xFFF83000	/* GPIO Control */
+#define	RTC_BA		0xFFF84000	/* Real Time Clock Control */
+#define	SCHI0_BA	0xFFF85000	/* Smart Card Host Interface 0 Control */
+#define	SCHI1_BA	0xFFF85800	/* Smart Card Host Interface 1 Control */
+#define	I2C0_BA		0xFFF86000	/* I2C 0 Control */
+#define	I2C1_BA		0xFFF86100	/* I2C 1 Control */
+#define	SSP_BA		0xFFF86200	/* Synchronous Serial Port */
+#define	PWM_BA		0xFFF87000	/* Pulse Width Modulation Control */
+#define	KPI_BA		0xFFF88000	/* Keypad Interface Control */
+#define	PS2_BA		0xFFF89000	/* PS2 Interface Control */
+
+/* System Manager Control Registers  */
+#define	REG_PDID	(GCR_BA+0x0000)	/* Product Identifier */
+#define	REG_ARBCON	(GCR_BA+0x0004)	/* Arbitration Control */
+#define	REG_PLLCON	(GCR_BA+0x0008)	/* PLL Control */
+#define	REG_CLKSEL	(GCR_BA+0x000C)	/* Clock Select */
+#define	REG_PLLCON2	(GCR_BA+0x0010)	/* PLL Control2 */
+#define	REG_I2SCKCON	(GCR_BA+0x0014)	/* Audio IIS Clock Control */
+#define	REG_IRQWAKECON	(GCR_BA+0x0020)	/* IRQ Wakeup Control */
+#define	REG_IRQWAKEFLAG	(GCR_BA+0x0024)	/* IRQ Wakeup Flag */
+#define	REG_PMCON	(GCR_BA+0x0028)	/* Power Manager */
+#define	REG_USBTXRCON	(GCR_BA+0x0030)	/* USB transceiver */
+
+/* Memory Control Registers */
+#define	REG_EBICON	(EBI_BA+0x000)	/* EBI control */
+#define	REG_ROMCON	(EBI_BA+0x004)	/* ROM/FLASH control */
+#define	REG_SDCONF0	(EBI_BA+0x008)	/* SDRAM bank 0 configuration */
+#define	REG_SDCONF1	(EBI_BA+0x00C)	/* SDRAM bank 1 configuration */
+#define	REG_SDTIME0	(EBI_BA+0x010)	/* SDRAM bank 0 timing control */
+#define	REG_SDTIME1	(EBI_BA+0x014)	/* SDRAM bank 1 timing control */
+#define	REG_EXT0CON	(EBI_BA+0x018)	/* External I/O 0 control */
+#define	REG_EXT1CON	(EBI_BA+0x01C)	/* External I/O 1 control */
+#define	REG_EXT2CON	(EBI_BA+0x020)	/* External I/O 2 control */
+#define	REG_EXT3CON	(EBI_BA+0x024)	/* External I/O 3 control */
+
+/* Cache Control Registers */
+#define REG_CAHCNF	(CACHE_BA+0x000)/* Cache configuration */
+#define REG_CAHCON	(CACHE_BA+0x004)/* Cache control */
+#define REG_CAHADR	(CACHE_BA+0x008)/* Cache address */
+
+/* MAC Control registers*/
+#define	REG_CAMCMR	(EMC_BA+0x000)	/* CAM Command */
+#define	REG_CAMEN	(EMC_BA+0x004)	/* CAM Enable */
+#define	REG_CAM0M_Base	(EMC_BA+0x008)
+#define	REG_CAM0L_Base	(EMC_BA+0x00c)
+
+#define	REG_TXDLSA	(EMC_BA+0x088)	/* Transmit Descriptor Link List Start Address Register */
+#define	REG_RXDLSA	(EMC_BA+0x08C)	/* Receive Descriptor Link List Start Address Register */
+#define	REG_MCMDR	(EMC_BA+0x090)	/* MAC Command */
+#define	REG_MIID	(EMC_BA+0x094)	/* MII Management Data */
+#define	REG_MIIDA	(EMC_BA+0x098)	/* MII Management Control and Address */
+#define	REG_FFTCR	(EMC_BA+0x09C)	/* FIFO Threshold Control */
+#define	REG_TSDR	(EMC_BA+0x0a0)	/* Transmit Start Demand */
+#define	REG_RSDR	(EMC_BA+0x0a4)	/* Receive Start Demand */
+#define	REG_DMARFC	(EMC_BA+0x0a8)	/* Maximum Receive Frame Control */
+#define	REG_MIEN	(EMC_BA+0x0ac)	/* MAC Interrupt Enable */
+
+/* MAC Status Registers */
+#define	REG_MISTA	(EMC_BA+0x0b0)	/* MAC Interrupt Status */
+#define	REG_MGSTA	(EMC_BA+0x0b4)	/* MAC General Status */
+#define	REG_MPCNT	(EMC_BA+0x0b8)	/* Missed Packet Count */
+#define	REG_MRPC	(EMC_BA+0x0bc)	/* MAC Receive Pause Count */
+#define	REG_MRPCC	(EMC_BA+0x0c0)	/* MAC Receive Pause Current Count */
+#define	REG_MREPC	(EMC_BA+0x0c4)	/* MAC Remote Pause Count */
+#define	REG_DMARFS	(EMC_BA+0x0c8)	/* DMA Receive Frame Status */
+#define	REG_CTXDSA	(EMC_BA+0x0cc)	/* Transmit Descriptor Start Address */
+#define	REG_CTXBSA	(EMC_BA+0x0d0)	/* Transmit Buffer Start Address */
+#define	REG_CRXDSA	(EMC_BA+0x0d4)	/* Receive Descriptor Start Address */
+#define	REG_CRXBSA	(EMC_BA+0x0d8)	/* Receive Buffer Start Address */
+
+/* MAC Diagnostic Registers */
+#define	REG_RXFSM	(EMC_BA+0x200)	/* Receive Finite State Machine */
+#define	REG_TXFSM	(EMC_BA+0x204)	/* Transmit Finite State Machine */
+#define	REG_FSM0	(EMC_BA+0x208)	/* Finite State Machine0 */
+#define	REG_FSM1	(EMC_BA+0x20c)	/* Finite State Machine1 */
+#define	REG_DCR		(EMC_BA+0x210)	/* Debug Configuration */
+#define	REG_DMMIR	(EMC_BA+0x214)	/* Debug Mode MAC Information */
+#define	REG_BISTR	(EMC_BA+0x300)	/* BIST Mode */
+
+/* USB Host Controller Registers */
+#define	REG_HcRevision		(USBH_BA+0x000)	/* Revision */
+#define	REG_HcControl		(USBH_BA+0x004)	/* Control */
+#define	REG_HcCommandStatus	(USBH_BA+0x008)	/* Command Status */
+#define	REG_HcInterruptStatus 	(USBH_BA+0x00C)	/* Interrupt Status */
+#define	REG_HcInterruptEnable	(USBH_BA+0x010)	/* Interrupt Enable */
+#define	REG_HcInterruptDisable	(USBH_BA+0x014)	/* Interrupt Disable */
+#define	REG_HcHCCA		(USBH_BA+0x018)	/* Communication Area */
+#define	REG_HcPeriodCurrentED	(USBH_BA+0x01C)	/* Period Current ED */
+#define	REG_HcControlHeadED	(USBH_BA+0x020)	/* Control Head ED */
+#define	REG_HcControlCurrentED	(USBH_BA+0x024)	/* Control Current ED */
+#define	REG_HcBulkHeadED	(USBH_BA+0x028)	/* Bulk Head ED */
+#define	REG_HcBulkCurrentED	(USBH_BA+0x02C)	/* Bulk Current ED */
+#define	REG_HcDoneHead		(USBH_BA+0x030)	/* Done Head */
+#define	REG_HcFmInterval	(USBH_BA+0x034)	/* Frame Interval */
+#define	REG_HcFrameRemaining	(USBH_BA+0x038)	/* Frame Remaining */
+#define	REG_HcFmNumber		(USBH_BA+0x03C)	/* Frame Number */
+#define	REG_HcPeriodicStart	(USBH_BA+0x040)	/* Periodic Start */
+#define	REG_HcLSThreshold	(USBH_BA+0x044)	/* Low Speed Threshold */
+#define	REG_HcRhDescriptorA	(USBH_BA+0x048)	/* Root Hub Descriptor A */
+#define	REG_HcRhDescriptorB	(USBH_BA+0x04C)	/* Root Hub Descriptor B */
+#define	REG_HcRhStatus		(USBH_BA+0x050)	/* Root Hub Status */
+#define	REG_HcRhPortStatus1	(USBH_BA+0x054)	/* Root Hub Port Status1 */
+#define	REG_HcRhPortStatus2	(USBH_BA+0x058)	/* Root Hub Port Status2 */
+
+/* USB Configuration Registers */
+#define TestModeEnable		(USBH_BA+0x200)	/* USB Test Mode Enable */
+#define OperationalModeEnable	(USBH_BA+0x204)	/* USB Operational Mode Enable*/
+
+/* UART0 Control Registers */
+#define	REG_UART0_TX	(UART0_BA+0x0)	/* TX buffer */
+#define	REG_UART0_RX	(UART0_BA+0x0)	/* RX buffer */
+#define	REG_UART0_LSB	(UART0_BA+0x0)	/* Divisor latch LSB */
+#define	REG_UART0_MSB	(UART0_BA+0x04)	/* Divisor latch MSB */
+#define	REG_UART0_IER	(UART0_BA+0x04)	/* Interrupt enable */
+#define	REG_UART0_IIR	(UART0_BA+0x08)	/* Interrupt ident */
+#define	REG_UART0_FCR	(UART0_BA+0x08)	/* FIFO control */
+#define	REG_UART0_LCR	(UART0_BA+0x0C)	/* Line control */
+#define	REG_UART0_LSR	(UART0_BA+0x14)	/* Line status */
+#define	REG_UART0_TOR	(UART0_BA+0x1C)	/* Time out */
+
+/* Timer Control Registers */
+#define	REG_TCR0	(TMR_BA+0x0)	/* Control Register 0 */
+#define	REG_TCR1	(TMR_BA+0x04)	/* Control Register 1 */
+#define	REG_TICR0	(TMR_BA+0x08)	/* Initial Control Register 0 */
+#define	REG_TICR1	(TMR_BA+0x0C)	/* Initial Control Register 1 */
+#define	REG_TDR0	(TMR_BA+0x10)	/* Data Register 0 */
+#define	REG_TDR1	(TMR_BA+0x14)	/* Data Register 1 */
+#define	REG_TISR	(TMR_BA+0x18)	/* Interrupt Status */
+#define REG_WTCR	(TMR_BA+0x1C)	/* Watchdog Timer Control */
+
+/* Advanced Interrupt Controller Registers */
+#define REG_AIC_IRSR    (AIC_BA+0x100)	/* Raw status */
+#define REG_AIC_IASR    (AIC_BA+0x104)	/* Active status */
+#define REG_AIC_ISR     (AIC_BA+0x108)	/* Status register */
+#define REG_AIC_IPER    (AIC_BA+0x10C)	/* Priority encoding */
+#define REG_AIC_ISNR    (AIC_BA+0x110)	/* Source number */
+#define REG_AIC_IMR     (AIC_BA+0x114)	/* Mask register */
+#define REG_AIC_OISR    (AIC_BA+0x118)	/* Interrupt status */
+#define REG_AIC_MECR    (AIC_BA+0x120)	/* Mask enable command */
+#define REG_AIC_MDCR    (AIC_BA+0x124)	/* Mask disable command */
+#define REG_AIC_SSCR    (AIC_BA+0x128)	/* Source set command */
+#define REG_AIC_SCCR    (AIC_BA+0x12C)	/* Source clear command */
+#define REG_AIC_EOSCR   (AIC_BA+0x130)	/* End of service command */
+#define REG_AIC_TEST    (AIC_BA+0x200)	/* ICE/Debug mode */
+
+/* General-Purpose Input/Output Controller Registers */
+ #define GPIO_OFFSET             0x10
+/* Port 0 */
+#define	REG_GPIO_CFG0		(GPIO_BA+0x0000)	/* Configuration */
+#define	REG_GPIO_DIR0		(GPIO_BA+0x0004)	/* Direction control */
+#define	REG_GPIO_DATAOUT0	(GPIO_BA+0x0008)	/* Data out */
+#define	REG_GPIO_DATAIN0        (GPIO_BA+0x000c)	/* Data input */
+/* Port 1 */
+#define	REG_GPIO_CFG1		(GPIO_BA+0x0010)	/* Configuration */
+#define	REG_GPIO_DIR1		(GPIO_BA+0x0014)	/* Direction control */
+#define	REG_GPIO_DATAOUT1	(GPIO_BA+0x0018)	/* Data out */
+#define	REG_GPIO_DATAIN1        (GPIO_BA+0x001c)	/* Data input */
+/* Port 2 */
+#define	REG_GPIO_CFG2		(GPIO_BA+0x0020)	/* Configuration */
+#define	REG_GPIO_DIR2		(GPIO_BA+0x0024)	/* Direction control */
+#define	REG_GPIO_DATAOUT2	(GPIO_BA+0x0028)	/* Data out */
+#define	REG_GPIO_DATAIN2        (GPIO_BA+0x002c)	/* Data input */
+/* Port 3 */
+#define	REG_GPIO_CFG3		(GPIO_BA+0x0030)	/* Configuration */
+#define	REG_GPIO_DIR3		(GPIO_BA+0x0034)	/* Direction control */
+#define	REG_GPIO_DATAOUT3	(GPIO_BA+0x0038)	/* Data out */
+#define	REG_GPIO_DATAIN3        (GPIO_BA+0x003c)	/* Data input */
+/* Port 4 */
+#define	REG_GPIO_CFG4		(GPIO_BA+0x0040)	/* Configuration */
+#define	REG_GPIO_DIR4		(GPIO_BA+0x0044)	/* Direction control */
+#define	REG_GPIO_DATAOUT4	(GPIO_BA+0x0048)	/* Data out */
+#define	REG_GPIO_DATAIN4        (GPIO_BA+0x004c)	/* Data input */
+/* Port 5 */
+#define	REG_GPIO_CFG5		(GPIO_BA+0x0050)	/* Configuration */
+#define	REG_GPIO_DIR5		(GPIO_BA+0x0054)	/* Direction control */
+#define	REG_GPIO_DATAOUT5	(GPIO_BA+0x0058)	/* Data out */
+#define	REG_GPIO_DATAIN5        (GPIO_BA+0x005c)	/* Data input */
+/* Port 6 */
+#define	REG_GPIO_CFG6		(GPIO_BA+0x0060)	/* Configuration */
+#define	REG_GPIO_DIR6		(GPIO_BA+0x0064)	/* Direction control */
+#define	REG_GPIO_DATAOUT6	(GPIO_BA+0x0068)	/* Data out */
+#define	REG_GPIO_DATAIN6        (GPIO_BA+0x006c)	/* Data input */
+
+#define	REG_GPIO_DBNCECON       (GPIO_BA+0x0070)	/* Input debounce */
+#define	REG_GPIO_XICFG		(GPIO_BA+0x0074) 	/* Interrupt Configure*/
+#define	REG_GPIO_XISTATUS	(GPIO_BA+0x0078) 	/* Interrupt Status */
+
+#endif /* _W90P710_H */
diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h
index 3056ca7..7f31b6c 100644
--- a/include/asm-arm/arch-arm720t/hardware.h
+++ b/include/asm-arm/arch-arm720t/hardware.h
@@ -36,6 +36,8 @@
  /* include armadillo specific hardware file if there was one */
  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
  /* include IntegratorCP/CM720T specific hardware file if there was one */
+#elif defined(CONFIG_W90P710)
+#include <asm-arm/arch-arm720t/W90P710.h>
  #else
  #error No hardware file defined for this configuration
  #endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index fec3a7e..4e17d22 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -46,6 +46,10 @@ static inline void sync(void)
  static inline void *
  map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
  {
+ #ifdef CONFIG_W90P710
+	if (flags == MAP_NOCACHE)
+		paddr |= 0x80000000;
+ #endif
  	return (void *)paddr;
  }

-- 
1.5.4.3