From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lbkql-0007cO-HV for qemu-devel@nongnu.org; Mon, 23 Feb 2009 19:08:39 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lbkqj-0007bX-Tz for qemu-devel@nongnu.org; Mon, 23 Feb 2009 19:08:39 -0500 Received: from [199.232.76.173] (port=39979 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lbkqj-0007bH-Ot for qemu-devel@nongnu.org; Mon, 23 Feb 2009 19:08:37 -0500 Received: from pop-knobcone.atl.sa.earthlink.net ([207.69.195.64]:39115) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Lbkqj-0003qD-Dk for qemu-devel@nongnu.org; Mon, 23 Feb 2009 19:08:37 -0500 Message-ID: <49A33A81.1070800@earthlink.net> Date: Mon, 23 Feb 2009 19:08:33 -0500 From: Robert Reif MIME-Version: 1.0 Subject: Re: [Qemu-devel] [5849] Change MMIO callbacks to use offsets, not absolute addresses. References: <200902231316.15214.paul@nowt.org> <49A2D23F.4020007@earthlink.net> <200902231704.28500.paul@codesourcery.com> In-Reply-To: <200902231704.28500.paul@codesourcery.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Paul Brook Paul Brook wrote: > On Monday 23 February 2009, Robert Reif wrote: > >> Paul Brook wrote: >> >>> Should be fixed now. >>> >> Not really. This fixes that specific case but it doesn't fix the >> general case where a hardware device needs to call do_unassigned_access >> because the hardware device still only has the offset. >> > > qemu has precisely zero devices that do this. > Just because something is currently not implemented properly is not a good reason to prevent a proper solution from ever being implemented in the future. > Also note that the current do_unaligned_access is bogus. You can't raise > synchronous exceptions from IO handlers. MMU exceptions have special handling > to make sure CPU state is consistent, and trap instructions explicitly > synchronise virtual CPU state before raising the exception. > > This is a problem that currently prevents sun open boot images from passing their built in self tests. The BIST does something that should generate an immediate response but the response doesn't happen until sometime later so the tests fail and then later complainswhen the response finally happens. This has been explained to me as a limitation of QEMU. >> You could store the physical base in each hardware device and recreate >> the physical address but that requires changing all hardware devices >> that need to do that. Why should the hardware drivers go through the >> trouble to recreate a physical address when just a few instructions >> before then the physical address was known but irreversibly destroyed >> when it was converted to an offset. >> > > Part of the reason for making this change is that it's a first step towards > making devices bus agnostic. If you have an IOMMU then the address the device > sees is different to the address the CPU sees. The most effective way to > avoid problems with this to have the device not know/care. > > Paul > > > > Sparc devices are passed in their physical addresses. They are currently hard wired because there is no proper bus/slot layer and only on-broad devices are implemented anyway. However each system may have the same hardware located at different locations so this may not be typical QEMU behavior. Real hardware deals with real addresses. An IOMMU is irrelevant because the IOMMU emulation will take care of the virtual to physical translation.