From: Jan Kiszka <jan.kiszka@siemens.com>
To: qemu-devel <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [RESEND][PATCH] x86: Enhanced dump of segment registers
Date: Wed, 11 Mar 2009 14:56:47 +0100 [thread overview]
Message-ID: <49B7C31F.5030201@siemens.com> (raw)
Parse the descriptor flags that segment registers refer to and show the
result in a more human-friendly format. The output of info registers eg.
then looks like this:
[...]
ES =007b 00000000 ffffffff 00cff300 DPL=3 DS [-WA]
CS =0060 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0068 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =007b 00000000 ffffffff 00cff300 DPL=3 DS [-WA]
FS =0000 00000000 00000000 00000000
GS =0033 b7dd66c0 ffffffff b7dff3dd DPL=3 DS [-WA]
LDT=0000 00000000 00000000 00008200 DPL=0 LDT
TR =0080 c06da700 0000206b 00008900 DPL=0 TSS32-avl
[...]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
target-i386/cpu.h | 3 ++
target-i386/helper.c | 62 +++++++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 58 insertions(+), 7 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 90bceab..f38f194 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -82,9 +82,10 @@
#define DESC_AVL_MASK (1 << 20)
#define DESC_P_MASK (1 << 15)
#define DESC_DPL_SHIFT 13
-#define DESC_DPL_MASK (1 << DESC_DPL_SHIFT)
+#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
#define DESC_S_MASK (1 << 12)
#define DESC_TYPE_SHIFT 8
+#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
#define DESC_A_MASK (1 << 8)
#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 8213703..d6a0e7d 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -570,6 +570,50 @@ static const char *cc_op_str[] = {
"SARQ",
};
+static void
+cpu_x86_dump_desc_flags(CPUState *env, FILE *f,
+ int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+ uint32_t dflags)
+{
+ if (!(env->hflags & HF_PE_MASK) || !(dflags & DESC_P_MASK))
+ goto done;
+
+ cpu_fprintf(f, " DPL=%d ", (dflags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
+ if (dflags & DESC_S_MASK) {
+ if (dflags & DESC_CS_MASK) {
+ cpu_fprintf(f, (dflags & DESC_L_MASK) ? "CS64" :
+ ((dflags & DESC_B_MASK) ? "CS32" : "CS16"));
+ cpu_fprintf(f, " [%c%c", (dflags & DESC_C_MASK) ? 'C' : '-',
+ (dflags & DESC_R_MASK) ? 'R' : '-');
+ } else {
+ cpu_fprintf(f, (dflags & DESC_B_MASK) ? "DS " : "DS16");
+ cpu_fprintf(f, " [%c%c", (dflags & DESC_E_MASK) ? 'E' : '-',
+ (dflags & DESC_W_MASK) ? 'W' : '-');
+ }
+ cpu_fprintf(f, "%c]", (dflags & DESC_A_MASK) ? 'A' : '-');
+ } else {
+ static const char *sys_type_name[2][16] = {
+ { /* 32 bit mode */
+ "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
+ "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
+ "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
+ "CallGate32", "Reserved", "IntGate32", "TrapGate32"
+ },
+ { /* 64 bit mode */
+ "<hiword>", "Reserved", "LDT", "Reserved", "Reserved"
+ "Reserved", "Reserved", "Reserved", "Reserved",
+ "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
+ "Reserved", "IntGate64", "TrapGate64"
+ }
+ };
+ cpu_fprintf(f, sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
+ [(dflags & DESC_TYPE_MASK)
+ >> DESC_TYPE_SHIFT]);
+ }
+done:
+ cpu_fprintf(f, "\n");
+}
+
void cpu_dump_state(CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
@@ -652,23 +696,26 @@ void cpu_dump_state(CPUState *env, FILE *f,
if (env->hflags & HF_LMA_MASK) {
for(i = 0; i < 6; i++) {
SegmentCache *sc = &env->segs[i];
- cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
+ cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x",
seg_name[i],
sc->selector,
sc->base,
sc->limit,
sc->flags);
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, sc->flags);
}
- cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
+ cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x",
env->ldt.selector,
env->ldt.base,
env->ldt.limit,
env->ldt.flags);
- cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, env->ldt.flags);
+ cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x",
env->tr.selector,
env->tr.base,
env->tr.limit,
env->tr.flags);
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, env->tr.flags);
cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
env->gdt.base, env->gdt.limit);
cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
@@ -687,23 +734,26 @@ void cpu_dump_state(CPUState *env, FILE *f,
{
for(i = 0; i < 6; i++) {
SegmentCache *sc = &env->segs[i];
- cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
+ cpu_fprintf(f, "%s =%04x %08x %08x %08x",
seg_name[i],
sc->selector,
(uint32_t)sc->base,
sc->limit,
sc->flags);
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, sc->flags);
}
- cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
+ cpu_fprintf(f, "LDT=%04x %08x %08x %08x",
env->ldt.selector,
(uint32_t)env->ldt.base,
env->ldt.limit,
env->ldt.flags);
- cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, env->ldt.flags);
+ cpu_fprintf(f, "TR =%04x %08x %08x %08x",
env->tr.selector,
(uint32_t)env->tr.base,
env->tr.limit,
env->tr.flags);
+ cpu_x86_dump_desc_flags(env, f, cpu_fprintf, env->tr.flags);
cpu_fprintf(f, "GDT= %08x %08x\n",
(uint32_t)env->gdt.base, env->gdt.limit);
cpu_fprintf(f, "IDT= %08x %08x\n",
next reply other threads:[~2009-03-11 13:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-11 13:56 Jan Kiszka [this message]
2009-03-11 16:10 ` [Qemu-devel] [RESEND][PATCH] x86: Enhanced dump of segment registers Jamie Lokier
2009-03-11 16:31 ` [Qemu-devel] " Jan Kiszka
2009-03-11 16:40 ` Jamie Lokier
2009-03-11 19:18 ` malc
2009-03-11 19:24 ` Jan Kiszka
2009-03-12 14:37 ` Avi Kivity
2009-03-12 14:57 ` Jan Kiszka
2009-03-12 17:58 ` Jamie Lokier
2009-03-12 18:21 ` Jan Kiszka
2009-03-11 19:40 ` [Qemu-devel] [PATCH v2] " Jan Kiszka
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