Re: [Qemu-devel] [PATCH 13/25] Add 21272 chipset (memory and pci controller for alpha)

[Robert Reif <reif@earthlink.net>]

Tristan Gingold wrote:
> Signed-off-by: Tristan Gingold <gingold@adacore.com>
> ---
>  hw/21272.c |  831 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/pci.h   |    8 +
>  2 files changed, 839 insertions(+), 0 deletions(-)
>  create mode 100644 hw/21272.c
>
> diff --git a/hw/21272.c b/hw/21272.c
> new file mode 100644
> index 0000000..267b682
> --- /dev/null
> +++ b/hw/21272.c
> @@ -0,0 +1,831 @@
> +/*
> + * Qemu 21272 (Tsunami/Typhoon) chipset emulation.
> + *
> + * Copyright (c) 2009 AdaCore
> + *
> + * Written by Tristan Gingold.
> + *
> + * This work is licensed under the GNU GPL license version 2 or later.
> + */
> +#include "hw.h"
> +#include "devices.h"
> +#include "pci.h"
> +
> +//#define DEBUG_CCHIP
> +//#define DEBUG_PCHIP
> +//#define DEBUG_DCHIP
> +//#define DEBUG_PCICFG
> +
> +typedef struct PchipState PchipState;
> +struct PchipState {
> +    /* IntAck handler.  */
> +    int (*iack_handler)(void *);
> +    void *iack_handler_param;
> +
> +    PCIBus *pci;
> +
> +    /* Pchip id.  */
> +    int num;
> +
> +    /* Used to reconstruct 64bits accesses.  Low long word first.  */
> +    uint32_t data;
> +
> +    uint32_t wsba[3];
> +    uint64_t wsba3;
> +    uint32_t wsm[3];
> +    uint32_t wsm3;
> +    uint64_t tba[3];
> +    uint64_t tba3;
> +    uint32_t perrmask;
> +    /* pctl */
> +    unsigned char ptevrfy;
> +    unsigned char mwin;
> +    unsigned char hole;
> +    unsigned char chaindis;
> +};
> +
> +struct TyphoonState {
> +    qemu_irq *irqs;
> +    qemu_irq *intim_irq;
> +    CPUState *cpu[4];
> +
> +    /* Used to reconstruct 64bits accesses.  Low long word first.  */
> +    uint32_t data;
> +
> +    unsigned char misc_rev;
> +    unsigned char misc_abw;
> +    unsigned char misc_abt;
> +
> +    int b_irq[4];
> +
> +    uint64_t dim[4];
> +    uint64_t dir[4];
> +    uint64_t drir;
> +    uint64_t aar[4];
> +
> +    /* dchip */
> +    uint64_t csc;
> +    uint64_t str;
> +
> +    PchipState pchip[2];
> +};
> +
> +
This looks like a perfect candidate for 64 bit I/O.  
http://lists.gnu.org/archive/html/qemu-devel/2009-03/msg00918.html