From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH] fix c/s 18938 Date: Fri, 27 Mar 2009 17:08:00 +0000 Message-ID: <49CD1600.76E4.0078.0@novell.com> References: <49CD0E0F.76E4.0078.0@novell.com> <200903271749.15350.Christoph.Egger@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <200903271749.15350.Christoph.Egger@amd.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Christoph Egger , xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org >>> Christoph Egger 27.03.09 17:49 >>> >On Friday 27 March 2009 17:34:07 Jan Beulich wrote: >> - * Currently Intel extended MSR (32/64) including all gp registers >> - * and E(R)DI, E(R)BP, E(R)SP, E(R)FLAGS, E(R)IP, E(R)MISC, only = 10 >> - * of them might be useful. So expend this array to 10. >> - */ >> - struct mcinfo_msr mc_msr[10]; >> + * Currently Intel extended MSR (32/64) include all gp registers >> + * and E(R)FLAGS, E(R)IP, E(R)MISC, up to 11/19 of them might be >> + * useful at present. So expand this array to 16/32 to leave room. >> + */ >> + struct mcinfo_msr mc_msr[sizeof(void *) * 4]; > >Please make this a fixed sized array. There are users like Oracle who run >a 32bit PAE Dom0 on a 64bit Xen ... And you expect a 32-bit kernel to be able to make sense of the MSRs corresponding to 64-bit-only registers? But you remind me that I failed to handle the difference in size of that array for 32-on-64 - I really need to check why the structure layout checking logic didn't catch the difference in size. Oh, right, sizeof(void = *) needs special treatment (and I really don#t want to sue sizeof(long) here due to the implied dependency on the OS ABI). Jan