From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?ISO-8859-1?Q?Daniel_Gl=F6ckner?= <dg@emlix.com>
Subject: Re: [PATCH v2] tlv320aic3x: disable ADC/DAC
 while	changing clock
Date: Thu, 02 Apr 2009 12:45:03 +0200
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On 04/02/2009 12:34 PM, Mark Brown wrote:
> On Thu, Apr 02, 2009 at 10:39:12AM +0300, Jarkko Nikula wrote:
>> My two cents: It supports different sampling rates for ADC and DAC but
>> I don't believe there is practical use or HW doing this. In this setup
>> there is separate word clock signal on GPIO1 for ADC.
> =

> Hrm, that's fairly common for hardware - even with shared LRCLK many
> devices will be able to support asymmetric rates providing there are
> enough BCLKs to drive the data.  Presumably the only limit in the codec
> itself is going to be that whatever the PLL is set for will be the
> maximum.

It's only the tlv320aic33 that has GPIO pins.
On the other supported devices the datasheet says on register 98:
"Reserved. Write only 0 to these bits"

While we're at it, there are other registers where we are already writing
values !=3D 0 which are not allowed on aic31 and aic32.

  Daniel

-- =

Dipl.-Math. Daniel Gl=F6ckner, emlix GmbH, http://www.emlix.com
Fon +49 551 30664-0, Fax -11, Bahnhofsallee 1b, 37081 G=F6ttingen, Germany
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