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Tue, 17 Mar 2026 22:45:11 -0700 (PDT) Received: from [172.16.20.13] ([136.226.252.245]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b06e5f0ac2sm13463195ad.52.2026.03.17.22.45.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2026 22:45:10 -0700 (PDT) Message-ID: <49b79a0d-844b-4fee-bccb-706187ed76d1@gmail.com> Date: Wed, 18 Mar 2026 11:15:29 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: tessolveupstream@gmail.com Subject: Re: [PATCH v2 0/2] drm: bridge: ti-sn65dsi83: Improve dual-link LVDS support To: Luca Ceresoli , Marek Vasut , andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, valentin@compulab.co.il, philippe.schenker@toradex.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260312043743.261475-1-tessolveupstream@gmail.com> <9f694b2d-44bc-46ad-8aa3-b464c2f0da13@nabladev.com> <176ed865-11a6-42de-89e0-06951b59a430@gmail.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 12-03-2026 21:19, Luca Ceresoli wrote: > Hello Sudarshan, > > and thanks Marek for copying me, I hadn't noticed this series. > > On Thu Mar 12, 2026 at 1:35 PM CET, tessolveupstream wrote: > > [...] > >>> +CC Luca >>> >>> You might want to look at recently posted: >>> >>> [PATCH 2/3] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output >> >> Thanks for pointing this out. >> I tried applying the patch “[PATCH 2/3] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output” on top of the current tree and >> removed the changes that I had previously added in the driver. >> However, with this patch applied, I am currently seeing only the backlight turning on and no image on the LVDS panel. >> For reference, the LVDS panel used on our platform is G133HAN01.1 and the >> DSI-to-dual-link LVDS bridge is SN65DSI84ZXHR. > > Thanks for having tried. > > Can you please test with both the fixes in the series applied + the test > pattern feature and report the results you get with and without test > pattern enabled? > > The patches to apply are: > > - https://lore.kernel.org/all/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com/ > - https://lore.kernel.org/all/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-2-2e15f5a9a6a0@bootlin.com/ > - https://lore.kernel.org/lkml/20260309-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v2-1-e6aaa7e1d181@bootlin.com/ > Thanks for the suggestions. I tested the three patches together as mentioned, but the LVDS panel still only shows the backlight and no image. I also tried removing the test-pattern patch and retesting with only the remaining two fixes, but the result remained the same — only the backlight turns on and no image is displayed. >> During our earlier debugging, we went through several trial-and-error >> iterations and also received support from TI. According to TI, when >> operating in dual-link mode the horizontal timing parameters must be >> divided by two before being written to the device. Without this >> adjustment, the panel either does not light up or shows corrupted output. >> >> TI also shared a set of recommended register settings for dual-link mode, >> which were derived using the TI DSI-Tuner tool. These settings helped us >> get the panel working on our hardware during testing. >> For reference, the register configuration suggested by TI is as follows: >> >> regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 0x05); >> regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); >> regmap_write(ctx->regmap, REG_DSI_CLK, 0x53); >> regmap_write(ctx->regmap, REG_LVDS_FMT, 0x6f); >> regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x00); >> regmap_write(ctx->regmap, >> REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 0x00); >> regmap_write(ctx->regmap, >> REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH, 0x00); >> regmap_write(ctx->regmap, >> REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 0x10); >> regmap_write(ctx->regmap, >> REG_VID_CHA_HORIZONTAL_BACK_PORCH, 0x28); >> regmap_write(ctx->regmap, >> REG_VID_CHA_VERTICAL_BACK_PORCH, 0x00); >> regmap_write(ctx->regmap, >> REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 0x00); >> regmap_write(ctx->regmap, >> REG_VID_CHA_VERTICAL_FRONT_PORCH, 0x00); >> >> If it would help, we can test any proposed changes on our hardware. > > The first thing I suggest doing on your side is testing with the 3 patches > mentioned above. > > If you display works, good! Let us know (you can also add your Tested-by / > Reviewed-by tags to the test_pattern patch too if applicable). > > If it doesn't work, compare the individual register values to find the > differences, try to figure out why the working setting works and how to > apply that change to the driver in away that keeps other boards > working. You're welcome to come back here to discuss it in case you can't > find out on your own. > I tested the three patches as suggested, but the panel still shows only the backlight with no visible image. I’m unsure how to translate the working register values into a generic fix based on display timings. Any guidance on the right direction would be helpful. > Hope this helps, > Luca > > -- > Luca Ceresoli, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com