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([2804:7f0:bcc0:8aab:3274:6ac1:70e0:b96f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe8284f116sm6084471a91.49.2025.02.28.03.10.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Feb 2025 03:10:48 -0800 (PST) Message-ID: <49d7ff1f-6fcb-45ef-88d5-cee1558d0711@ventanamicro.com> Date: Fri, 28 Feb 2025 08:10:45 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/3] target/riscv/kvm: reset time changes To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com References: <20250221122623.495188-1-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250221122623.495188-1-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Hi Alistair, Can you please take a look in this series? This will collide with another series that are changing KVM CSRs that will require a rebase. Might as well do a rebase on top of this set too since it's fully acked already. Thanks, Daniel On 2/21/25 9:26 AM, Daniel Henrique Barboza wrote: > Hi, > > In this version the following changes were made, based on feedback from > Drew in v1: > > - patch 2: reworked. Instead of using a different existing 'env' field > to get/put the 'sie' CSR, we're adding a new helper that contains all > reset vals for the KVM CSRs we support > - patch 3: reworked. Add two KVM CSRs from the KVM UAPI that we're not > using. > > Link to v1: https://lore.kernel.org/qemu-riscv/20250220161313.127376-1-dbarboza@ventanamicro.com/ > > Patches based on alistair/riscv-to-apply.next. > > Daniel Henrique Barboza (3): > target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold > target/riscv/kvm: add kvm_riscv_reset_regs_csr() > target/riscv/kvm: add missing KVM CSRs > > target/riscv/cpu.c | 9 +++++---- > target/riscv/kvm/kvm-cpu.c | 32 +++++++++++++++++++++----------- > 2 files changed, 26 insertions(+), 15 deletions(-) >