* [Qemu-devel] Commit messages
[not found] <200905080136.n481aDrS017783@d03av01.boulder.ibm.com>
@ 2009-05-10 5:57 ` Andreas Färber
2009-05-11 10:35 ` Gerd Hoffmann
0 siblings, 1 reply; 6+ messages in thread
From: Andreas Färber @ 2009-05-10 5:57 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Hello Anthony,
Could you please make the commit messages include the summary of which
files were changed?
Thanks,
Andreas
Am 08.05.2009 um 03:36 schrieb Anthony Liguori:
> From: Paul Brook <paul@codesourcery.com>
>
> Signed-off-by: Paul Brook <paul@codesourcery.com>
>
> diff --git a/hw/an5206.c b/hw/an5206.c
> index a5e352e..7088466 100644
> --- a/hw/an5206.c
> +++ b/hw/an5206.c
> @@ -41,7 +41,7 @@ static void an5206_init(ram_addr_t ram_size, int
> vga_ram_size,
> cpu_model = "m5206";
> env = cpu_init(cpu_model);
> if (!env) {
> - cpu_abort(env, "Unable to find m68k CPU definition\n");
> + hw_error("Unable to find m68k CPU definition\n");
> }
>
> /* Initialize CPU registers. */
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index 8e61b6e..2f484e1 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -343,7 +343,7 @@ static uint32_t gic_dist_readb(void *opaque,
> target_phys_addr_t offset)
> }
> return res;
> bad_reg:
> - cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n",
> (int)offset);
> + hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
> return 0;
> }
>
> @@ -505,7 +505,7 @@ static void gic_dist_writeb(void *opaque,
> target_phys_addr_t offset,
> gic_update(s);
> return;
> bad_reg:
> - cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n",
> (int)offset);
> + hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
> }
>
> static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
> @@ -587,8 +587,7 @@ static uint32_t gic_cpu_read(gic_state *s, int
> cpu, int offset)
> case 0x18: /* Highest Pending Interrupt */
> return s->current_pending[cpu];
> default:
> - cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -609,8 +608,7 @@ static void gic_cpu_write(gic_state *s, int cpu,
> int offset, uint32_t value)
> case 0x10: /* End Of Interrupt */
> return gic_complete_irq(s, cpu, value & 0x3ff);
> default:
> - cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
> - (int)offset);
> + hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
> return;
> }
> gic_update(s);
> diff --git a/hw/arm_pic.c b/hw/arm_pic.c
> index c9f3cad..f44568c 100644
> --- a/hw/arm_pic.c
> +++ b/hw/arm_pic.c
> @@ -39,7 +39,7 @@ static void arm_pic_cpu_handler(void *opaque, int
> irq, int level)
> cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
> break;
> default:
> - cpu_abort(env, "arm_pic_cpu_handler: Bad interrput line %d
> \n", irq);
> + hw_error("arm_pic_cpu_handler: Bad interrput line %d\n",
> irq);
> }
> }
>
> diff --git a/hw/arm_timer.c b/hw/arm_timer.c
> index c93f333..0eff7b9 100644
> --- a/hw/arm_timer.c
> +++ b/hw/arm_timer.c
> @@ -62,8 +62,7 @@ static uint32_t arm_timer_read(void *opaque,
> target_phys_addr_t offset)
> return 0;
> return s->int_level;
> default:
> - cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -130,8 +129,7 @@ static void arm_timer_write(void *opaque,
> target_phys_addr_t offset,
> arm_timer_recalibrate(s, 0);
> break;
> default:
> - cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x
> \n",
> - (int)offset);
> + hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
> }
> arm_timer_update(s);
> }
> @@ -290,8 +288,9 @@ static uint32_t icp_pit_read(void *opaque,
> target_phys_addr_t offset)
>
> /* ??? Don't know the PrimeCell ID for this device. */
> n = offset >> 8;
> - if (n > 3)
> - cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
> + if (n > 3) {
> + hw_error("sp804_read: Bad timer %d\n", n);
> + }
>
> return arm_timer_read(s->timer[n], offset & 0xff);
> }
> @@ -303,8 +302,9 @@ static void icp_pit_write(void *opaque,
> target_phys_addr_t offset,
> int n;
>
> n = offset >> 8;
> - if (n > 3)
> - cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
> + if (n > 3) {
> + hw_error("sp804_write: Bad timer %d\n", n);
> + }
>
> arm_timer_write(s->timer[n], offset & 0xff, value);
> }
> diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
> index 86d0cf8..306ac38 100644
> --- a/hw/armv7m_nvic.c
> +++ b/hw/armv7m_nvic.c
> @@ -102,7 +102,7 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
>
> irq = gic_acknowledge_irq(s->gic, 0);
> if (irq == 1023)
> - cpu_abort(cpu_single_env, "Interrupt but no vector\n");
> + hw_error("Interrupt but no vector\n");
> if (irq >= 32)
> irq -= 16;
> return irq;
> @@ -221,8 +221,7 @@ static uint32_t nvic_readl(void *opaque,
> uint32_t offset)
> return val;
> case 0xd28: /* Configurable Fault Status. */
> /* TODO: Implement Fault Status. */
> - cpu_abort(cpu_single_env,
> - "Not implemented: Configurable Fault Status.");
> + hw_error("Not implemented: Configurable Fault Status.");
> return 0;
> case 0xd2c: /* Hard Fault Status. */
> case 0xd30: /* Debug Fault Status. */
> @@ -260,7 +259,7 @@ static uint32_t nvic_readl(void *opaque,
> uint32_t offset)
> /* TODO: Implement debug registers. */
> default:
> bad_reg:
> - cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n",
> offset);
> + hw_error("NVIC: Bad read offset 0x%x\n", offset);
> }
> }
>
> @@ -324,10 +323,10 @@ static void nvic_writel(void *opaque, uint32_t
> offset, uint32_t value)
> case 0xd0c: /* Application Interrupt/Reset Control. */
> if ((value >> 16) == 0x05fa) {
> if (value & 2) {
> - cpu_abort(cpu_single_env, "VECTCLRACTIVE not
> implemented");
> + hw_error("VECTCLRACTIVE not implemented");
> }
> if (value & 5) {
> - cpu_abort(cpu_single_env, "System reset");
> + hw_error("System reset");
> }
> }
> break;
> @@ -362,7 +361,7 @@ static void nvic_writel(void *opaque, uint32_t
> offset, uint32_t value)
> goto bad_reg;
> default:
> bad_reg:
> - cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n",
> offset);
> + hw_error("NVIC: Bad write offset 0x%x\n", offset);
> }
> }
>
> @@ -402,7 +401,7 @@ qemu_irq *armv7m_nvic_init(CPUState *env)
> s->gic->nvic = s;
> s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick,
> s);
> if (env->v7m.nvic)
> - cpu_abort(env, "CPU can only have one NVIC\n");
> + hw_error("CPU can only have one NVIC\n");
> env->v7m.nvic = s;
> register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
> return s->gic->in;
> diff --git a/hw/cbus.c b/hw/cbus.c
> index ba8afe5..b60ec05 100644
> --- a/hw/cbus.c
> +++ b/hw/cbus.c
> @@ -63,8 +63,7 @@ static void cbus_io(struct cbus_priv_s *s)
> s->slave[s->addr]->io(s->slave[s->addr]->opaque,
> s->rw, s->reg, &s->val);
> else
> - cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
> - __FUNCTION__, s->addr);
> + hw_error("%s: bad slave address %i\n", __FUNCTION__, s-
> >addr);
> }
>
> static void cbus_cycle(struct cbus_priv_s *s)
> @@ -301,8 +300,7 @@ static inline uint16_t retu_read(struct
> cbus_retu_s *s, int reg)
> return 0x0000;
>
> default:
> - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
> - __FUNCTION__, reg);
> + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
> }
> }
>
> @@ -375,8 +373,7 @@ static inline void retu_write(struct cbus_retu_s
> *s, int reg, uint16_t val)
> break;
>
> default:
> - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
> - __FUNCTION__, reg);
> + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
> }
> }
>
> @@ -542,8 +539,7 @@ static inline uint16_t tahvo_read(struct
> cbus_tahvo_s *s, int reg)
> return 0x0000;
>
> default:
> - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
> - __FUNCTION__, reg);
> + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
> }
> }
>
> @@ -593,8 +589,7 @@ static inline void tahvo_write(struct
> cbus_tahvo_s *s, int reg, uint16_t val)
> break;
>
> default:
> - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
> - __FUNCTION__, reg);
> + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
> }
> }
>
> diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
> index e4bc824..12dd78d 100644
> --- a/hw/etraxfs_dma.c
> +++ b/hw/etraxfs_dma.c
> @@ -562,10 +562,7 @@ static inline int channel_in_run(struct
> fs_dma_ctrl *ctrl, int c)
>
> static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
> {
> - struct fs_dma_ctrl *ctrl = opaque;
> - CPUState *env = ctrl->env;
> - cpu_abort(env, "Unsupported short access. reg="
> TARGET_FMT_plx "\n",
> - addr);
> + hw_error("Unsupported short access. reg=" TARGET_FMT_plx
> "\n", addr);
> return 0;
> }
>
> @@ -600,10 +597,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
> static void
> dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
> {
> - struct fs_dma_ctrl *ctrl = opaque;
> - CPUState *env = ctrl->env;
> - cpu_abort(env, "Unsupported short access. reg="
> TARGET_FMT_plx "\n",
> - addr);
> + hw_error("Unsupported short access. reg=" TARGET_FMT_plx
> "\n", addr);
> }
>
> static void
> diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
> index 9e5cbb3..49e991c 100644
> --- a/hw/etraxfs_pic.c
> +++ b/hw/etraxfs_pic.c
> @@ -148,8 +148,7 @@ static void nmi_handler(void *opaque, int irq,
> int level)
>
> static void guru_handler(void *opaque, int irq, int level)
> {
> - struct fs_pic_state *fs = (void *)opaque;
> - cpu_abort(fs->env, "%s unsupported exception\n", __func__);
> + hw_error("%s unsupported exception\n", __func__);
> }
>
> struct etraxfs_pic *etraxfs_pic_init(CPUState *env,
> target_phys_addr_t base)
> diff --git a/hw/integratorcp.c b/hw/integratorcp.c
> index 68f34f6..2169f2c 100644
> --- a/hw/integratorcp.c
> +++ b/hw/integratorcp.c
> @@ -63,7 +63,7 @@ static uint32_t integratorcm_read(void *opaque,
> target_phys_addr_t offset)
> }
> case 6: /* CM_LMBUSCNT */
> /* ??? High frequency timer. */
> - cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
> + hw_error("integratorcm_read: CM_LMBUSCNT");
> case 7: /* CM_AUXOSC */
> return s->cm_auxosc;
> case 8: /* CM_SDRAM */
> @@ -72,7 +72,7 @@ static uint32_t integratorcm_read(void *opaque,
> target_phys_addr_t offset)
> return s->cm_init;
> case 10: /* CM_REFCT */
> /* ??? High frequency timer. */
> - cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
> + hw_error("integratorcm_read: CM_REFCT");
> case 12: /* CM_FLAGS */
> return s->cm_flags;
> case 14: /* CM_NVFLAGS */
> @@ -98,8 +98,8 @@ static uint32_t integratorcm_read(void *opaque,
> target_phys_addr_t offset)
> /* ??? Voltage control unimplemented. */
> return 0;
> default:
> - cpu_abort (cpu_single_env,
> - "integratorcm_read: Unimplemented offset 0x%x\n",
> (int)offset);
> + hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
> + (int)offset);
> return 0;
> }
> }
> @@ -117,7 +117,7 @@ static void
> integratorcm_do_remap(integratorcm_state *s, int flash)
> static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t
> value)
> {
> if (value & 8) {
> - cpu_abort(cpu_single_env, "Board reset\n");
> + hw_error("Board reset\n");
> }
> if ((s->cm_init ^ value) & 4) {
> integratorcm_do_remap(s, (value & 4) == 0);
> @@ -133,7 +133,7 @@ static void
> integratorcm_update(integratorcm_state *s)
> /* ??? The CPU irq/fiq is raised when either the core module or
> base PIC
> are active. */
> if (s->int_level & (s->irq_enabled | s->fiq_enabled))
> - cpu_abort(cpu_single_env, "Core module interrupt\n");
> + hw_error("Core module interrupt\n");
> }
>
> static void integratorcm_write(void *opaque, target_phys_addr_t
> offset,
> @@ -205,8 +205,8 @@ static void integratorcm_write(void *opaque,
> target_phys_addr_t offset,
> /* ??? Voltage control unimplemented. */
> break;
> default:
> - cpu_abort (cpu_single_env,
> - "integratorcm_write: Unimplemented offset 0x%x\n",
> (int)offset);
> + hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
> + (int)offset);
> break;
> }
> }
> @@ -401,8 +401,7 @@ static uint32_t icp_control_read(void *opaque,
> target_phys_addr_t offset)
> case 3: /* CP_DECODE */
> return 0x11;
> default:
> - cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x
> \n",
> - (int)offset);
> + hw_error("icp_control_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -417,8 +416,7 @@ static void icp_control_write(void *opaque,
> target_phys_addr_t offset,
> /* Nothing interesting implemented yet. */
> break;
> default:
> - cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x
> \n",
> - (int)offset);
> + hw_error("icp_control_write: Bad offset %x\n", (int)offset);
> }
> }
> static CPUReadMemoryFunc *icp_control_readfn[] = {
> diff --git a/hw/mcf5206.c b/hw/mcf5206.c
> index ee41a61..b570376 100644
> --- a/hw/mcf5206.c
> +++ b/hw/mcf5206.c
> @@ -61,11 +61,9 @@ static void
> m5206_timer_recalibrate(m5206_timer_state *s)
> prescale *= 16;
>
> if (mode == 3 || mode == 0)
> - cpu_abort(cpu_single_env,
> - "m5206_timer: mode %d not implemented\n", mode);
> + hw_error("m5206_timer: mode %d not implemented\n", mode);
> if ((s->tmr & TMR_FRR) == 0)
> - cpu_abort(cpu_single_env,
> - "m5206_timer: free running mode not implemented
> \n");
> + hw_error("m5206_timer: free running mode not implemented\n");
>
> /* Assume 66MHz system clock. */
> ptimer_set_freq(s->timer, 66000000 / prescale);
> @@ -296,7 +294,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state
> *s, uint32_t offset)
> case 0x170: return s->uivr[0];
> case 0x1b0: return s->uivr[1];
> }
> - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR read offset 0x%x", (int)offset);
> return 0;
> }
>
> @@ -350,7 +348,7 @@ static void m5206_mbar_write(m5206_mbar_state
> *s, uint32_t offset,
> s->uivr[1] = value;
> break;
> default:
> - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR write offset 0x%x", (int)offset);
> break;
> }
> }
> @@ -377,7 +375,7 @@ static uint32_t m5206_mbar_readb(void *opaque,
> target_phys_addr_t offset)
> m5206_mbar_state *s = (m5206_mbar_state *)opaque;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR read offset 0x%x", (int)offset);
> }
> if (m5206_mbar_width[offset >> 2] > 1) {
> uint16_t val;
> @@ -396,7 +394,7 @@ static uint32_t m5206_mbar_readw(void *opaque,
> target_phys_addr_t offset)
> int width;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR read offset 0x%x", (int)offset);
> }
> width = m5206_mbar_width[offset >> 2];
> if (width > 2) {
> @@ -420,7 +418,7 @@ static uint32_t m5206_mbar_readl(void *opaque,
> target_phys_addr_t offset)
> int width;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR read offset 0x%x", (int)offset);
> }
> width = m5206_mbar_width[offset >> 2];
> if (width < 4) {
> @@ -444,7 +442,7 @@ static void m5206_mbar_writeb(void *opaque,
> target_phys_addr_t offset,
> int width;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR write offset 0x%x", (int)offset);
> }
> width = m5206_mbar_width[offset >> 2];
> if (width > 1) {
> @@ -468,7 +466,7 @@ static void m5206_mbar_writew(void *opaque,
> target_phys_addr_t offset,
> int width;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR write offset 0x%x", (int)offset);
> }
> width = m5206_mbar_width[offset >> 2];
> if (width > 2) {
> @@ -496,7 +494,7 @@ static void m5206_mbar_writel(void *opaque,
> target_phys_addr_t offset,
> int width;
> offset &= 0x3ff;
> if (offset > 0x200) {
> - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x",
> (int)offset);
> + hw_error("Bad MBAR write offset 0x%x", (int)offset);
> }
> width = m5206_mbar_width[offset >> 2];
> if (width < 4) {
> diff --git a/hw/mcf5208.c b/hw/mcf5208.c
> index 5404dba..f22150a 100644
> --- a/hw/mcf5208.c
> +++ b/hw/mcf5208.c
> @@ -89,8 +89,7 @@ static void m5208_timer_write(void *opaque,
> target_phys_addr_t offset,
> case 4:
> break;
> default:
> - cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x
> %x\n",
> - (int)offset);
> + hw_error("m5208_timer_write: Bad offset 0x%x\n",
> (int)offset);
> break;
> }
> m5208_timer_update(s);
> @@ -114,8 +113,7 @@ static uint32_t m5208_timer_read(void *opaque,
> target_phys_addr_t addr)
> case 4:
> return ptimer_get_count(s->timer);
> default:
> - cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x
> \n",
> - (int)addr);
> + hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
> return 0;
> }
> }
> @@ -148,8 +146,7 @@ static uint32_t m5208_sys_read(void *opaque,
> target_phys_addr_t addr)
> return 0;
>
> default:
> - cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x
> \n",
> - (int)addr);
> + hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
> return 0;
> }
> }
> @@ -157,8 +154,7 @@ static uint32_t m5208_sys_read(void *opaque,
> target_phys_addr_t addr)
> static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
> uint32_t value)
> {
> - cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
> - (int)addr);
> + hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
> }
>
> static CPUReadMemoryFunc *m5208_sys_readfn[] = {
> diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
> index 1ca847b..81f179b 100644
> --- a/hw/mcf_fec.c
> +++ b/hw/mcf_fec.c
> @@ -246,8 +246,7 @@ static uint32_t mcf_fec_read(void *opaque,
> target_phys_addr_t addr)
> case 0x184: return s->etdsr;
> case 0x188: return s->emrbr;
> default:
> - cpu_abort(cpu_single_env, "mcf_fec_read: Bad address 0x%x\n",
> - (int)addr);
> + hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
> return 0;
> }
> }
> @@ -343,8 +342,7 @@ static void mcf_fec_write(void *opaque,
> target_phys_addr_t addr, uint32_t value)
> s->emrbr = value & 0x7f0;
> break;
> default:
> - cpu_abort(cpu_single_env, "mcf_fec_write Bad address 0x%x\n",
> - (int)addr);
> + hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
> }
> mcf_fec_update(s);
> }
> diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
> index 4e99aeb..ce378c2 100644
> --- a/hw/mcf_intc.c
> +++ b/hw/mcf_intc.c
> @@ -67,7 +67,7 @@ static uint32_t mcf_intc_read(void *opaque,
> target_phys_addr_t addr)
> case 0xe1: case 0xe2: case 0xe3: case 0xe4:
> case 0xe5: case 0xe6: case 0xe7:
> /* LnIACK */
> - cpu_abort(cpu_single_env, "mcf_intc_read: LnIACK not
> implemented\n");
> + hw_error("mcf_intc_read: LnIACK not implemented\n");
> default:
> return 0;
> }
> @@ -99,8 +99,7 @@ static void mcf_intc_write(void *opaque,
> target_phys_addr_t addr, uint32_t val)
> s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
> break;
> default:
> - cpu_abort(cpu_single_env, "mcf_intc_write: Bad write offset
> %d\n",
> - offset);
> + hw_error("mcf_intc_write: Bad write offset %d\n", offset);
> break;
> }
> mcf_intc_update(s);
> diff --git a/hw/mpcore.c b/hw/mpcore.c
> index 1d5fcc7..f90f73a 100644
> --- a/hw/mpcore.c
> +++ b/hw/mpcore.c
> @@ -195,8 +195,7 @@ static uint32_t mpcore_priv_read(void *opaque,
> target_phys_addr_t offset)
> return mpcore_timer_read(&s->timer[id], offset & 0xf);
> }
> bad_reg:
> - cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
> return 0;
> }
>
> @@ -241,8 +240,7 @@ static void mpcore_priv_write(void *opaque,
> target_phys_addr_t offset,
> }
> return;
> bad_reg:
> - cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
> }
>
> static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
> diff --git a/hw/musicpal.c b/hw/musicpal.c
> index fc227e9..b698610 100644
> --- a/hw/musicpal.c
> +++ b/hw/musicpal.c
> @@ -875,7 +875,7 @@ static void lcd_refresh(void *opaque)
> LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
> rgb_to_pixel32bgr : rgb_to_pixel32))
> default:
> - cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
> + hw_error("unsupported colour depth %i\n",
> ds_get_bits_per_pixel(s->ds));
> }
>
> diff --git a/hw/nand.c b/hw/nand.c
> index e73a1b8..935548e 100644
> --- a/hw/nand.c
> +++ b/hw/nand.c
> @@ -445,8 +445,7 @@ struct nand_flash_s *nand_init(int manf_id, int
> chip_id)
> int index;
>
> if (nand_flash_ids[chip_id].size == 0) {
> - cpu_abort(cpu_single_env, "%s: Unsupported NAND chip ID.\n",
> - __FUNCTION__);
> + hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
> }
>
> s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct
> nand_flash_s));
> @@ -475,8 +474,7 @@ struct nand_flash_s *nand_init(int manf_id, int
> chip_id)
> nand_init_2048(s);
> break;
> default:
> - cpu_abort(cpu_single_env, "%s: Unsupported NAND block size.
> \n",
> - __FUNCTION__);
> + hw_error("%s: Unsupported NAND block size.\n", __FUNCTION__);
> }
>
> pagesize = 1 << s->oob_shift;
> diff --git a/hw/nseries.c b/hw/nseries.c
> index dafc0ba..ab75183 100644
> --- a/hw/nseries.c
> +++ b/hw/nseries.c
> @@ -428,8 +428,7 @@ static uint32_t mipid_txrx(void *opaque,
> uint32_t cmd, int len)
> uint8_t ret;
>
> if (len > 9)
> - cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i
> \n",
> - __FUNCTION__, len);
> + hw_error("%s: FIXME: bad SPI word width %i\n",
> __FUNCTION__, len);
>
> if (s->p >= ARRAY_SIZE(s->resp))
> ret = 0;
> diff --git a/hw/omap1.c b/hw/omap1.c
> index c32d3f7..f6c0d9d 100644
> --- a/hw/omap1.c
> +++ b/hw/omap1.c
> @@ -1531,7 +1531,7 @@ static uint32_t omap_id_read(void *opaque,
> target_phys_addr_t addr)
> case omap1510:
> return 0x03310115;
> default:
> - cpu_abort(cpu_single_env, "%s: bad mpu model\n",
> __FUNCTION__);
> + hw_error("%s: bad mpu model\n", __FUNCTION__);
> }
> break;
>
> @@ -1542,7 +1542,7 @@ static uint32_t omap_id_read(void *opaque,
> target_phys_addr_t addr)
> case omap1510:
> return 0xfb47002f;
> default:
> - cpu_abort(cpu_single_env, "%s: bad mpu model\n",
> __FUNCTION__);
> + hw_error("%s: bad mpu model\n", __FUNCTION__);
> }
> break;
> }
> @@ -2775,15 +2775,14 @@ qemu_irq *omap_mpuio_in_get(struct
> omap_mpuio_s *s)
> void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq
> handler)
> {
> if (line >= 16 || line < 0)
> - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
> __FUNCTION__, line);
> + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
> s->handler[line] = handler;
> }
>
> void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int
> down)
> {
> if (row >= 5 || row < 0)
> - cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
> - __FUNCTION__, col, row);
> + hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
>
> if (down)
> s->buttons[row] |= 1 << col;
> @@ -2970,7 +2969,7 @@ qemu_irq *omap_gpio_in_get(struct omap_gpio_s
> *s)
> void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq
> handler)
> {
> if (line >= 16 || line < 0)
> - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
> __FUNCTION__, line);
> + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
> s->handler[line] = handler;
> }
>
> diff --git a/hw/omap2.c b/hw/omap2.c
> index 20b3811..82efbda 100644
> --- a/hw/omap2.c
> +++ b/hw/omap2.c
> @@ -1070,15 +1070,14 @@ struct omap_gpif_s *omap2_gpio_init(struct
> omap_target_agent_s *ta,
> qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
> {
> if (start >= s->modules * 32 || start < 0)
> - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
> - __FUNCTION__, start);
> + hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
> return s->module[start >> 5].in + (start & 31);
> }
>
> void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq
> handler)
> {
> if (line >= s->modules * 32 || line < 0)
> - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
> __FUNCTION__, line);
> + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
> s->module[line >> 5].handler[line & 31] = handler;
> }
>
> @@ -1399,8 +1398,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
> int chipselect)
> {
> if (chipselect < 0 || chipselect >= s->chnum)
> - cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
> - __FUNCTION__, chipselect);
> + hw_error("%s: Bad chipselect %i\n", __FUNCTION__,
> chipselect);
>
> s->ch[chipselect].txrx = txrx;
> s->ch[chipselect].opaque = opaque;
> @@ -2642,7 +2640,7 @@ static uint32_t omap_tap_read(void *opaque,
> target_phys_addr_t addr)
> case omap3430:
> return 0x1b7ae02f; /* ES 2 */
> default:
> - cpu_abort(cpu_single_env, "%s: Bad mpu model\n",
> __FUNCTION__);
> + hw_error("%s: Bad mpu model\n", __FUNCTION__);
> }
>
> case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
> @@ -2659,7 +2657,7 @@ static uint32_t omap_tap_read(void *opaque,
> target_phys_addr_t addr)
> case omap3430:
> return 0x000000f0;
> default:
> - cpu_abort(cpu_single_env, "%s: Bad mpu model\n",
> __FUNCTION__);
> + hw_error("%s: Bad mpu model\n", __FUNCTION__);
> }
>
> case 0x20c:
> @@ -2673,7 +2671,7 @@ static uint32_t omap_tap_read(void *opaque,
> target_phys_addr_t addr)
> case omap3430:
> return 0xcafeb7ae; /* ES 2 */
> default:
> - cpu_abort(cpu_single_env, "%s: Bad mpu model\n",
> __FUNCTION__);
> + hw_error("%s: Bad mpu model\n", __FUNCTION__);
> }
>
> case 0x218: /* DIE_ID_reg */
> diff --git a/hw/omap_clk.c b/hw/omap_clk.c
> index d7a5a57..fc86cf1 100644
> --- a/hw/omap_clk.c
> +++ b/hw/omap_clk.c
> @@ -1105,7 +1105,7 @@ struct clk *omap_findclk(struct
> omap_mpu_state_s *mpu, const char *name)
> for (i = mpu->clks; i->name; i ++)
> if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias,
> name)))
> return i;
> - cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
> + hw_error("%s: %s not found\n", __FUNCTION__, name);
> }
>
> void omap_clk_get(struct clk *clk)
> @@ -1116,8 +1116,7 @@ void omap_clk_get(struct clk *clk)
> void omap_clk_put(struct clk *clk)
> {
> if (!(clk->usecount --))
> - cpu_abort(cpu_single_env, "%s: %s is not in use\n",
> - __FUNCTION__, clk->name);
> + hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
> }
>
> static void omap_clk_update(struct clk *clk)
> diff --git a/hw/omap_dss.c b/hw/omap_dss.c
> index 4917c59..d8c2977 100644
> --- a/hw/omap_dss.c
> +++ b/hw/omap_dss.c
> @@ -1064,6 +1064,6 @@ struct omap_dss_s *omap_dss_init(struct
> omap_target_agent_s *ta,
> void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct
> rfbi_chip_s *chip)
> {
> if (cs < 0 || cs > 1)
> - cpu_abort(cpu_single_env, "%s: wrong CS %i\n",
> __FUNCTION__, cs);
> + hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
> s->rfbi.chip[cs] = chip;
> }
> diff --git a/hw/onenand.c b/hw/onenand.c
> index 6aacff6..4a5c7bd 100644
> --- a/hw/onenand.c
> +++ b/hw/onenand.c
> @@ -156,8 +156,7 @@ static void onenand_reset(struct onenand_s *s,
> int cold)
> memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
>
> if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
> - cpu_abort(cpu_single_env, "%s: Loading the BootRAM
> failed.\n",
> - __FUNCTION__);
> + hw_error("%s: Loading the BootRAM failed.\n",
> __FUNCTION__);
> }
> }
>
> @@ -500,7 +499,7 @@ static uint32_t onenand_read(void *opaque,
> target_phys_addr_t addr)
> case 0xff02: /* ECC Result of spare area data */
> case 0xff03: /* ECC Result of main area data */
> case 0xff04: /* ECC Result of spare area data */
> - cpu_abort(cpu_single_env, "%s: imeplement ECC\n",
> __FUNCTION__);
> + hw_error("%s: imeplement ECC\n", __FUNCTION__);
> return 0x0000;
> }
>
> diff --git a/hw/pl011.c b/hw/pl011.c
> index 468d48a..3a4e149 100644
> --- a/hw/pl011.c
> +++ b/hw/pl011.c
> @@ -103,7 +103,7 @@ static uint32_t pl011_read(void *opaque,
> target_phys_addr_t offset)
> case 18: /* UARTDMACR */
> return s->dmacr;
> default:
> - cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl011_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -175,10 +175,10 @@ static void pl011_write(void *opaque,
> target_phys_addr_t offset,
> case 18: /* UARTDMACR */
> s->dmacr = value;
> if (value & 3)
> - cpu_abort(cpu_single_env, "PL011: DMA not implemented
> \n");
> + hw_error("PL011: DMA not implemented\n");
> break;
> default:
> - cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl011_write: Bad offset %x\n", (int)offset);
> }
> }
>
> diff --git a/hw/pl022.c b/hw/pl022.c
> index 90f4f0f..3027bcf 100644
> --- a/hw/pl022.c
> +++ b/hw/pl022.c
> @@ -168,8 +168,7 @@ static uint32_t pl022_read(void *opaque,
> target_phys_addr_t offset)
> /* Not implemented. */
> return 0;
> default:
> - cpu_abort (cpu_single_env, "pl022_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("pl022_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -211,12 +210,12 @@ static void pl022_write(void *opaque,
> target_phys_addr_t offset,
> pl022_update(s);
> break;
> case 0x20: /* DMACR */
> - if (value)
> - cpu_abort (cpu_single_env, "pl022: DMA not implemented
> \n");
> + if (value) {
> + hw_error("pl022: DMA not implemented\n");
> + }
> break;
> default:
> - cpu_abort (cpu_single_env, "pl022_write: Bad offset %x\n",
> - (int)offset);
> + hw_error("pl022_write: Bad offset %x\n", (int)offset);
> }
> }
>
> diff --git a/hw/pl031.c b/hw/pl031.c
> index 8c62995..3f8bfaa 100644
> --- a/hw/pl031.c
> +++ b/hw/pl031.c
> @@ -119,8 +119,7 @@ static uint32_t pl031_read(void *opaque,
> target_phys_addr_t offset)
> (int)offset);
> break;
> default:
> - cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
> - (int)offset);
> + hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
> break;
> }
>
> @@ -168,8 +167,7 @@ static void pl031_write(void * opaque,
> target_phys_addr_t offset,
> break;
>
> default:
> - cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
> - (int)offset);
> + hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
> break;
> }
> }
> @@ -195,8 +193,9 @@ void pl031_init(uint32_t base, qemu_irq irq)
> s = qemu_mallocz(sizeof(pl031_state));
>
> iomemtype = cpu_register_io_memory(0, pl031_readfn,
> pl031_writefn, s);
> - if (iomemtype == -1)
> - cpu_abort(cpu_single_env, "pl031_init: Can't register I/O
> memory\n");
> + if (iomemtype == -1) {
> + hw_error("pl031_init: Can't register I/O memory\n");
> + }
>
> cpu_register_physical_memory(base, 0x00001000, iomemtype);
>
> diff --git a/hw/pl050.c b/hw/pl050.c
> index 0ab60bf..0a7ef83 100644
> --- a/hw/pl050.c
> +++ b/hw/pl050.c
> @@ -79,7 +79,7 @@ static uint32_t pl050_read(void *opaque,
> target_phys_addr_t offset)
> case 4: /* KMIIR */
> return s->pending | 2;
> default:
> - cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl050_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -107,7 +107,7 @@ static void pl050_write(void *opaque,
> target_phys_addr_t offset,
> s->clk = value;
> return;
> default:
> - cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl050_write: Bad offset %x\n", (int)offset);
> }
> }
> static CPUReadMemoryFunc *pl050_readfn[] = {
> diff --git a/hw/pl061.c b/hw/pl061.c
> index fab99d4..71141ad 100644
> --- a/hw/pl061.c
> +++ b/hw/pl061.c
> @@ -126,8 +126,7 @@ static uint32_t pl061_read(void *opaque,
> target_phys_addr_t offset)
> case 0x524: /* Commit */
> return s->cr;
> default:
> - cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("pl061_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -199,8 +198,7 @@ static void pl061_write(void *opaque,
> target_phys_addr_t offset,
> s->cr = value;
> break;
> default:
> - cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
> - (int)offset);
> + hw_error("pl061_write: Bad offset %x\n", (int)offset);
> }
> pl061_update(s);
> }
> diff --git a/hw/pl080.c b/hw/pl080.c
> index e4d7e17..d18445b 100644
> --- a/hw/pl080.c
> +++ b/hw/pl080.c
> @@ -93,7 +93,7 @@ static void pl080_run(pl080_state *s)
> if ((s->conf & PL080_CONF_E) == 0)
> return;
>
> -cpu_abort(cpu_single_env, "DMA active\n");
> +hw_error("DMA active\n");
> /* If we are already in the middle of a DMA operation then
> indicate that
> there may be new DMA requests and return immediately. */
> if (s->running) {
> @@ -111,7 +111,7 @@ again:
> continue;
> flow = (ch->conf >> 11) & 7;
> if (flow >= 4) {
> - cpu_abort(cpu_single_env,
> + hw_error(
> "pl080_run: Peripheral flow control not
> implemented\n");
> }
> src_id = (ch->conf >> 1) & 0x1f;
> @@ -242,7 +242,7 @@ static uint32_t pl080_read(void *opaque,
> target_phys_addr_t offset)
> return s->sync;
> default:
> bad_offset:
> - cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl080_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -288,13 +288,12 @@ static void pl080_write(void *opaque,
> target_phys_addr_t offset,
> case 10: /* SoftLBReq */
> case 11: /* SoftLSReq */
> /* ??? Implement these. */
> - cpu_abort(cpu_single_env, "pl080_write: Soft DMA not
> implemented\n");
> + hw_error("pl080_write: Soft DMA not implemented\n");
> break;
> case 12: /* Configuration */
> s->conf = value;
> if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
> - cpu_abort(cpu_single_env,
> - "pl080_write: Big-endian DMA not implemented
> \n");
> + hw_error("pl080_write: Big-endian DMA not implemented
> \n");
> }
> pl080_run(s);
> break;
> @@ -303,7 +302,7 @@ static void pl080_write(void *opaque,
> target_phys_addr_t offset,
> break;
> default:
> bad_offset:
> - cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl080_write: Bad offset %x\n", (int)offset);
> }
> pl080_update(s);
> }
> diff --git a/hw/pl110.c b/hw/pl110.c
> index f21b63b..f37b20a 100644
> --- a/hw/pl110.c
> +++ b/hw/pl110.c
> @@ -267,7 +267,7 @@ static uint32_t pl110_read(void *opaque,
> target_phys_addr_t offset)
> case 12: /* LCDLPCURR */
> return s->lpbase;
> default:
> - cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl110_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -333,7 +333,7 @@ static void pl110_write(void *opaque,
> target_phys_addr_t offset,
> pl110_update(s);
> break;
> default:
> - cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl110_write: Bad offset %x\n", (int)offset);
> }
> }
>
> diff --git a/hw/pl181.c b/hw/pl181.c
> index 8583490..b0709dc 100644
> --- a/hw/pl181.c
> +++ b/hw/pl181.c
> @@ -332,7 +332,7 @@ static uint32_t pl181_read(void *opaque,
> target_phys_addr_t offset)
> return value;
> }
> default:
> - cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl181_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -403,7 +403,7 @@ static void pl181_write(void *opaque,
> target_phys_addr_t offset,
> }
> break;
> default:
> - cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl181_write: Bad offset %x\n", (int)offset);
> }
> pl181_update(s);
> }
> diff --git a/hw/pl190.c b/hw/pl190.c
> index b5863f7..d7eb695 100644
> --- a/hw/pl190.c
> +++ b/hw/pl190.c
> @@ -137,7 +137,7 @@ static uint32_t pl190_read(void *opaque,
> target_phys_addr_t offset)
> case 13: /* DEFVECTADDR */
> return s->vect_addr[16];
> default:
> - cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n",
> (int)offset);
> + hw_error("pl190_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -190,11 +190,12 @@ static void pl190_write(void *opaque,
> target_phys_addr_t offset, uint32_t val)
> s->default_addr = val;
> break;
> case 0xc0: /* ITCR */
> - if (val)
> - cpu_abort(cpu_single_env, "pl190: Test mode not
> implemented\n");
> + if (val) {
> + hw_error("pl190: Test mode not implemented\n");
> + }
> break;
> default:
> - cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n",
> (int)offset);
> + hw_error("pl190_write: Bad offset %x\n", (int)offset);
> return;
> }
> pl190_update(s);
> diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
> index f67b727..0fe8c5f 100644
> --- a/hw/ppc_newworld.c
> +++ b/hw/ppc_newworld.c
> @@ -146,7 +146,7 @@ static void ppc_core99_init (ram_addr_t
> ram_size, int vga_ram_size,
> /* Load OpenBIOS (ELF) */
> bios_size = load_elf(buf, 0, NULL, NULL, NULL);
> if (bios_size < 0 || bios_size > BIOS_SIZE) {
> - cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n",
> buf);
> + hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
> exit(1);
> }
>
> @@ -190,8 +190,7 @@ static void ppc_core99_init (ram_addr_t
> ram_size, int vga_ram_size,
> kernel_base,
> ram_size - kernel_base);
> if (kernel_size < 0) {
> - cpu_abort(env, "qemu: could not load kernel '%s'\n",
> - kernel_filename);
> + hw_error("qemu: could not load kernel '%s'\n",
> kernel_filename);
> exit(1);
> }
> /* load initrd */
> @@ -200,8 +199,8 @@ static void ppc_core99_init (ram_addr_t
> ram_size, int vga_ram_size,
> initrd_size = load_image_targphys(initrd_filename,
> initrd_base,
> ram_size - initrd_base);
> if (initrd_size < 0) {
> - cpu_abort(env, "qemu: could not load initial ram
> disk '%s'\n",
> - initrd_filename);
> + hw_error("qemu: could not load initial ram disk
> '%s'\n",
> + initrd_filename);
> exit(1);
> }
> } else {
> @@ -278,7 +277,7 @@ static void ppc_core99_init (ram_addr_t
> ram_size, int vga_ram_size,
> break;
> #endif /* defined(TARGET_PPC64) */
> default:
> - cpu_abort(env, "Bus model not supported on mac99 machine
> \n");
> + hw_error("Bus model not supported on mac99 machine\n");
> exit(1);
> }
> }
> diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
> index 06c77b4..aa56d50 100644
> --- a/hw/ppc_oldworld.c
> +++ b/hw/ppc_oldworld.c
> @@ -179,7 +179,7 @@ static void ppc_heathrow_init (ram_addr_t
> ram_size, int vga_ram_size,
> /* Load OpenBIOS (ELF) */
> bios_size = load_elf(buf, 0, NULL, NULL, NULL);
> if (bios_size < 0 || bios_size > BIOS_SIZE) {
> - cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n",
> buf);
> + hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
> exit(1);
> }
>
> @@ -222,7 +222,7 @@ static void ppc_heathrow_init (ram_addr_t
> ram_size, int vga_ram_size,
> kernel_base,
> ram_size - kernel_base);
> if (kernel_size < 0) {
> - cpu_abort(env, "qemu: could not load kernel '%s'\n",
> + hw_error("qemu: could not load kernel '%s'\n",
> kernel_filename);
> exit(1);
> }
> @@ -232,8 +232,8 @@ static void ppc_heathrow_init (ram_addr_t
> ram_size, int vga_ram_size,
> initrd_size = load_image_targphys(initrd_filename,
> initrd_base,
> ram_size - initrd_base);
> if (initrd_size < 0) {
> - cpu_abort(env, "qemu: could not load initial ram
> disk '%s'\n",
> - initrd_filename);
> + hw_error("qemu: could not load initial ram disk
> '%s'\n",
> + initrd_filename);
> exit(1);
> }
> } else {
> @@ -288,15 +288,13 @@ static void ppc_heathrow_init (ram_addr_t
> ram_size, int vga_ram_size,
> ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
> break;
> default:
> - cpu_abort(env, "Bus model not supported on OldWorld Mac
> machine\n");
> - exit(1);
> + hw_error("Bus model not supported on OldWorld Mac
> machine\n");
> }
> }
>
> /* init basic PC hardware */
> if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
> - cpu_abort(env, "Only 6xx bus is supported on heathrow
> machine\n");
> - exit(1);
> + hw_error("Only 6xx bus is supported on heathrow machine\n");
> }
> pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
> pci_bus = pci_grackle_init(0xfec00000, pic);
> diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
> index 0e2d581..020b5b7 100644
> --- a/hw/ppc_prep.c
> +++ b/hw/ppc_prep.c
> @@ -595,11 +595,10 @@ static void ppc_prep_init (ram_addr_t
> ram_size, int vga_ram_size,
> bios_size = load_image_targphys(buf, bios_addr, bios_size);
> }
> if (bios_size < 0 || bios_size > BIOS_SIZE) {
> - cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n",
> buf);
> - exit(1);
> + hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
> }
> if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
> - cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
> + hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
> }
>
> if (linux_boot) {
> @@ -608,8 +607,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
> int vga_ram_size,
> kernel_size = load_image_targphys(kernel_filename,
> kernel_base,
> ram_size - kernel_base);
> if (kernel_size < 0) {
> - cpu_abort(env, "qemu: could not load kernel '%s'\n",
> - kernel_filename);
> + hw_error("qemu: could not load kernel '%s'\n",
> kernel_filename);
> exit(1);
> }
> /* load initrd */
> @@ -618,9 +616,8 @@ static void ppc_prep_init (ram_addr_t ram_size,
> int vga_ram_size,
> initrd_size = load_image_targphys(initrd_filename,
> initrd_base,
> ram_size - initrd_base);
> if (initrd_size < 0) {
> - cpu_abort(env, "qemu: could not load initial ram
> disk '%s'\n",
> + hw_error("qemu: could not load initial ram disk
> '%s'\n",
> initrd_filename);
> - exit(1);
> }
> } else {
> initrd_base = 0;
> @@ -648,8 +645,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
> int vga_ram_size,
>
> isa_mem_base = 0xc0000000;
> if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
> - cpu_abort(env, "Only 6xx bus is supported on PREP machine
> \n");
> - exit(1);
> + hw_error("Only 6xx bus is supported on PREP machine\n");
> }
> i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
> pci_bus = pci_prep_init(i8259);
> diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
> index 8c47189..2d38cc3 100644
> --- a/hw/pxa2xx_dma.c
> +++ b/hw/pxa2xx_dma.c
> @@ -301,8 +301,7 @@ static uint32_t pxa2xx_dma_read(void *opaque,
> target_phys_addr_t offset)
> }
> }
>
> - cpu_abort(cpu_single_env,
> - "%s: Bad offset 0x" TARGET_FMT_plx "\n",
> __FUNCTION__, offset);
> + hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__,
> offset);
> return 7;
> }
>
> @@ -321,8 +320,8 @@ static void pxa2xx_dma_write(void *opaque,
>
> if (value & DRCMR_MAPVLD)
> if ((value & DRCMR_CHLNUM) > s->channels)
> - cpu_abort(cpu_single_env, "%s: Bad DMA channel %i\n",
> - __FUNCTION__, value & DRCMR_CHLNUM);
> + hw_error("%s: Bad DMA channel %i\n",
> + __FUNCTION__, value & DRCMR_CHLNUM);
>
> s->req[channel] = value;
> break;
> @@ -401,21 +400,20 @@ static void pxa2xx_dma_write(void *opaque,
> break;
> }
> fail:
> - cpu_abort(cpu_single_env, "%s: Bad offset " TARGET_FMT_plx
> "\n",
> - __FUNCTION__, offset);
> + hw_error("%s: Bad offset " TARGET_FMT_plx "\n",
> __FUNCTION__, offset);
> }
> }
>
> static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t
> offset)
> {
> - cpu_abort(cpu_single_env, "%s: Bad access width\n",
> __FUNCTION__);
> + hw_error("%s: Bad access width\n", __FUNCTION__);
> return 5;
> }
>
> static void pxa2xx_dma_writebad(void *opaque,
> target_phys_addr_t offset, uint32_t value)
> {
> - cpu_abort(cpu_single_env, "%s: Bad access width\n",
> __FUNCTION__);
> + hw_error("%s: Bad access width\n", __FUNCTION__);
> }
>
> static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = {
> @@ -530,8 +528,7 @@ void pxa2xx_dma_request(struct
> pxa2xx_dma_state_s *s, int req_num, int on)
> {
> int ch;
> if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
> - cpu_abort(cpu_single_env,
> - "%s: Bad DMA request %i\n", __FUNCTION__, req_num);
> + hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
>
> if (!(s->req[req_num] & DRCMR_MAPVLD))
> return;
> diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
> index 0f3dcb1..9d939cb 100644
> --- a/hw/pxa2xx_gpio.c
> +++ b/hw/pxa2xx_gpio.c
> @@ -179,8 +179,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque,
> target_phys_addr_t offset)
> return s->status[bank];
>
> default:
> - cpu_abort(cpu_single_env,
> - "%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
>
> return 0;
> @@ -234,8 +233,7 @@ static void pxa2xx_gpio_write(void *opaque,
> break;
>
> default:
> - cpu_abort(cpu_single_env,
> - "%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
> }
>
> diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
> index 522c9c1..965fa35 100644
> --- a/hw/pxa2xx_keypad.c
> +++ b/hw/pxa2xx_keypad.c
> @@ -209,8 +209,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque,
> target_phys_addr_t offset)
> return s->kpkdi;
> break;
> default:
> - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
> - __FUNCTION__, offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
>
> return 0;
> @@ -254,8 +253,7 @@ static void pxa2xx_keypad_write(void *opaque,
> break;
>
> default:
> - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
> - __FUNCTION__, offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
> }
>
> diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
> index 2bd0ec0..4b9f428 100644
> --- a/hw/pxa2xx_lcd.c
> +++ b/hw/pxa2xx_lcd.c
> @@ -400,8 +400,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque,
> target_phys_addr_t offset)
>
> default:
> fail:
> - cpu_abort(cpu_single_env,
> - "%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
>
> return 0;
> @@ -556,8 +555,7 @@ static void pxa2xx_lcdc_write(void *opaque,
>
> default:
> fail:
> - cpu_abort(cpu_single_env,
> - "%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
> }
>
> diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
> index 46258b4..74e3627 100644
> --- a/hw/pxa2xx_mmci.c
> +++ b/hw/pxa2xx_mmci.c
> @@ -266,8 +266,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque,
> target_phys_addr_t offset)
> case MMC_BLKS_REM:
> return s->numblk;
> default:
> - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
> - __FUNCTION__, offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
>
> return 0;
> @@ -379,8 +378,7 @@ static void pxa2xx_mmci_write(void *opaque,
> break;
>
> default:
> - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
> - __FUNCTION__, offset);
> + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__,
> offset);
> }
> }
>
> diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
> index dd17fcf..52cf58e 100644
> --- a/hw/pxa2xx_timer.c
> +++ b/hw/pxa2xx_timer.c
> @@ -205,8 +205,7 @@ static uint32_t pxa2xx_timer_read(void *opaque,
> target_phys_addr_t offset)
> return s->snapshot;
> default:
> badreg:
> - cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
> - REG_FMT "\n", offset);
> + hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n",
> offset);
> }
>
> return 0;
> @@ -315,8 +314,7 @@ static void pxa2xx_timer_write(void *opaque,
> target_phys_addr_t offset,
> break;
> default:
> badreg:
> - cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
> - REG_FMT "\n", offset);
> + hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n",
> offset);
> }
> }
>
> diff --git a/hw/sh_timer.c b/hw/sh_timer.c
> index da3ace2..1a1404c 100644
> --- a/hw/sh_timer.c
> +++ b/hw/sh_timer.c
> @@ -72,8 +72,7 @@ static uint32_t sh_timer_read(void *opaque,
> target_phys_addr_t offset)
> if (s->feat & TIMER_FEAT_CAPT)
> return s->tcpr;
> default:
> - cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
> - (int)offset);
> + hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
> return 0;
> }
> }
> @@ -110,23 +109,20 @@ static void sh_timer_write(void *opaque,
> target_phys_addr_t offset,
> case 4: freq >>= 10; break;
> case 6:
> case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
> - default: cpu_abort (cpu_single_env,
> - "sh_timer_write: Reserved TPSC value\n"); break;
> + default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
> }
> switch ((value & TIMER_TCR_CKEG) >> 3) {
> case 0: break;
> case 1:
> case 2:
> case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
> - default: cpu_abort (cpu_single_env,
> - "sh_timer_write: Reserved CKEG value\n"); break;
> + default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
> }
> switch ((value & TIMER_TCR_ICPE) >> 6) {
> case 0: break;
> case 2:
> case 3: if (s->feat & TIMER_FEAT_CAPT) break;
> - default: cpu_abort (cpu_single_env,
> - "sh_timer_write: Reserved ICPE value\n"); break;
> + default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
> }
> if ((value & TIMER_TCR_UNF) == 0)
> s->int_level = 0;
> @@ -134,14 +130,12 @@ static void sh_timer_write(void *opaque,
> target_phys_addr_t offset,
> value &= ~TIMER_TCR_UNF;
>
> if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
> - cpu_abort (cpu_single_env,
> - "sh_timer_write: Reserved ICPF value\n");
> + hw_error("sh_timer_write: Reserved ICPF value\n");
>
> value &= ~TIMER_TCR_ICPF; /* capture not supported */
>
> if (value & TIMER_TCR_RESERVED)
> - cpu_abort (cpu_single_env,
> - "sh_timer_write: Reserved TCR bits set\n");
> + hw_error("sh_timer_write: Reserved TCR bits set\n");
> s->tcr = value;
> ptimer_set_limit(s->timer, s->tcor, 0);
> ptimer_set_freq(s->timer, freq);
> @@ -156,8 +150,7 @@ static void sh_timer_write(void *opaque,
> target_phys_addr_t offset,
> break;
> }
> default:
> - cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
> - (int)offset);
> + hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
> }
> sh_timer_update(s);
> }
> @@ -234,8 +227,7 @@ static uint32_t tmu012_read(void *opaque,
> target_phys_addr_t offset)
>
> if (offset >= 0x20) {
> if (!(s->feat & TMU012_FEAT_3CHAN))
> - cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x
> \n",
> - (int)offset);
> + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
> return sh_timer_read(s->timer[2], offset - 0x20);
> }
>
> @@ -251,8 +243,7 @@ static uint32_t tmu012_read(void *opaque,
> target_phys_addr_t offset)
> if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
> return s->tocr;
>
> - cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
> - (int)offset);
> + hw_error("tmu012_write: Bad offset %x\n", (int)offset);
> return 0;
> }
>
> @@ -267,8 +258,7 @@ static void tmu012_write(void *opaque,
> target_phys_addr_t offset,
>
> if (offset >= 0x20) {
> if (!(s->feat & TMU012_FEAT_3CHAN))
> - cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x
> \n",
> - (int)offset);
> + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
> sh_timer_write(s->timer[2], offset - 0x20, value);
> return;
> }
> @@ -290,7 +280,7 @@ static void tmu012_write(void *opaque,
> target_phys_addr_t offset,
> sh_timer_start_stop(s->timer[2], value & (1 << 2));
> else
> if (value & (1 << 2))
> - cpu_abort (cpu_single_env, "tmu012_write: Bad
> channel\n");
> + hw_error("tmu012_write: Bad channel\n");
>
> s->tstr = value;
> return;
> diff --git a/hw/smc91c111.c b/hw/smc91c111.c
> index 9f567ab..e294f51 100644
> --- a/hw/smc91c111.c
> +++ b/hw/smc91c111.c
> @@ -413,8 +413,7 @@ static void smc91c111_writeb(void *opaque,
> target_phys_addr_t offset,
> }
> break;
> }
> - cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
> - s->bank, (int)offset);
> + hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank,
> (int)offset);
> }
>
> static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t
> offset)
> @@ -554,8 +553,7 @@ static uint32_t smc91c111_readb(void *opaque,
> target_phys_addr_t offset)
> }
> break;
> }
> - cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
> - s->bank, (int)offset);
> + hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank,
> (int)offset);
> return 0;
> }
>
> diff --git a/hw/stellaris.c b/hw/stellaris.c
> index cefad85..3a06c12 100644
> --- a/hw/stellaris.c
> +++ b/hw/stellaris.c
> @@ -94,8 +94,7 @@ static void gptm_reload(gptm_state *s, int n, int
> reset)
> } else if (s->mode[n] == 0xa) {
> /* PWM mode. Not implemented. */
> } else {
> - cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
> - s->mode[n]);
> + hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
> }
> s->tick[n] = tick;
> qemu_mod_timer(s->timer[n], tick);
> @@ -137,8 +136,7 @@ static void gptm_tick(void *opaque)
> } else if (s->mode[n] == 0xa) {
> /* PWM mode. Not implemented. */
> } else {
> - cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
> - s->mode[n]);
> + hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
> }
> gptm_update_irq(s);
> }
> @@ -184,9 +182,9 @@ static uint32_t gptm_read(void *opaque,
> target_phys_addr_t offset)
> if (s->control == 1)
> return s->rtc;
> case 0x4c: /* TBR */
> - cpu_abort(cpu_single_env, "TODO: Timer value read\n");
> + hw_error("TODO: Timer value read\n");
> default:
> - cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n",
> (int)offset);
> + hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
> return 0;
> }
> }
> @@ -266,7 +264,7 @@ static void gptm_write(void *opaque,
> target_phys_addr_t offset, uint32_t value)
> s->match_prescale[0] = value;
> break;
> default:
> - cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n",
> (int)offset);
> + hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
> }
> gptm_update_irq(s);
> }
> @@ -500,7 +498,7 @@ static uint32_t ssys_read(void *opaque,
> target_phys_addr_t offset)
> case 0x1e4: /* USER1 */
> return s->user1;
> default:
> - cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n",
> (int)offset);
> + hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
> return 0;
> }
> }
> @@ -577,7 +575,7 @@ static void ssys_write(void *opaque,
> target_phys_addr_t offset, uint32_t value)
> s->ldoarst = value;
> break;
> default:
> - cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n",
> (int)offset);
> + hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
> }
> ssys_update(s);
> }
> @@ -724,8 +722,7 @@ static uint32_t stellaris_i2c_read(void *opaque,
> target_phys_addr_t offset)
> case 0x20: /* MCR */
> return s->mcr;
> default:
> - cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x
> %x\n",
> - (int)offset);
> + hw_error("strllaris_i2c_read: Bad offset 0x%x\n",
> (int)offset);
> return 0;
> }
> }
> @@ -801,15 +798,15 @@ static void stellaris_i2c_write(void *opaque,
> target_phys_addr_t offset,
> break;
> case 0x20: /* MCR */
> if (value & 1)
> - cpu_abort(cpu_single_env,
> + hw_error(
> "stellaris_i2c_write: Loopback not implemented
> \n");
> if (value & 0x20)
> - cpu_abort(cpu_single_env,
> + hw_error(
> "stellaris_i2c_write: Slave mode not
> implemented\n");
> s->mcr = value & 0x31;
> break;
> default:
> - cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset
> 0x%x\n",
> + hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
> (int)offset);
> }
> stellaris_i2c_update(s);
> @@ -1036,7 +1033,7 @@ static uint32_t stellaris_adc_read(void
> *opaque, target_phys_addr_t offset)
> case 0x30: /* SAC */
> return s->sac;
> default:
> - cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x
> %x\n",
> + hw_error("strllaris_adc_read: Bad offset 0x%x\n",
> (int)offset);
> return 0;
> }
> @@ -1057,7 +1054,7 @@ static void stellaris_adc_write(void *opaque,
> target_phys_addr_t offset,
> return;
> case 0x04: /* SSCTL */
> if (value != 6) {
> - cpu_abort(cpu_single_env, "ADC: Unimplemented
> sequence %x\n",
> + hw_error("ADC: Unimplemented sequence %x\n",
> value);
> }
> s->ssctl[n] = value;
> @@ -1070,8 +1067,7 @@ static void stellaris_adc_write(void *opaque,
> target_phys_addr_t offset,
> case 0x00: /* ACTSS */
> s->actss = value & 0xf;
> if (value & 0xe) {
> - cpu_abort(cpu_single_env,
> - "Not implemented: ADC sequencers 1-3\n");
> + hw_error("Not implemented: ADC sequencers 1-3\n");
> }
> break;
> case 0x08: /* IM */
> @@ -1093,14 +1089,13 @@ static void stellaris_adc_write(void
> *opaque, target_phys_addr_t offset,
> s->sspri = value;
> break;
> case 0x28: /* PSSI */
> - cpu_abort(cpu_single_env, "Not implemented: ADC sample
> initiate\n");
> + hw_error("Not implemented: ADC sample initiate\n");
> break;
> case 0x30: /* SAC */
> s->sac = value;
> break;
> default:
> - cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset
> 0x%x\n",
> - (int)offset);
> + hw_error("stellaris_adc_write: Bad offset 0x%x\n",
> (int)offset);
> }
> stellaris_adc_update(s);
> }
> diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
> index a4c2011..c9a0909 100644
> --- a/hw/stellaris_enet.c
> +++ b/hw/stellaris_enet.c
> @@ -190,8 +190,7 @@ static uint32_t stellaris_enet_read(void
> *opaque, target_phys_addr_t offset)
> case 0x3c: /* Undocuented: Timestamp? */
> return 0;
> default:
> - cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset
> %x\n",
> - (int)offset);
> + hw_error("stellaris_enet_read: Bad offset %x\n",
> (int)offset);
> return 0;
> }
> }
> @@ -298,8 +297,7 @@ static void stellaris_enet_write(void *opaque,
> target_phys_addr_t offset,
> /* Ignored. */
> break;
> default:
> - cpu_abort (cpu_single_env, "stellaris_enet_write: Bad
> offset %x\n",
> - (int)offset);
> + hw_error("stellaris_enet_write: Bad offset %x\n",
> (int)offset);
> }
> }
>
> diff --git a/hw/tsc210x.c b/hw/tsc210x.c
> index 41d374f..55e1214 100644
> --- a/hw/tsc210x.c
> +++ b/hw/tsc210x.c
> @@ -893,7 +893,7 @@ static uint16_t tsc210x_read(struct
> tsc210x_state_s *s)
> ret = tsc2102_audio_register_read(s, s->offset);
> break;
> default:
> - cpu_abort(cpu_single_env, "tsc210x_read: wrong memory page
> \n");
> + hw_error("tsc210x_read: wrong memory page\n");
> }
>
> tsc210x_pin_update(s);
> @@ -930,8 +930,7 @@ static void tsc210x_write(struct tsc210x_state_s
> *s, uint16_t value)
> tsc2102_audio_register_write(s, s->offset, value);
> break;
> default:
> - cpu_abort(cpu_single_env,
> - "tsc210x_write: wrong memory page
> \n");
> + hw_error("tsc210x_write: wrong memory page\n");
> }
>
> tsc210x_pin_update(s);
> @@ -945,8 +944,7 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t
> value, int len)
> uint32_t ret = 0;
>
> if (len != 16)
> - cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i
> \n",
> - __FUNCTION__, len);
> + hw_error("%s: FIXME: bad SPI word width %i\n",
> __FUNCTION__, len);
>
> /* TODO: sequential reads etc - how do we make sure the host
> doesn't
> * unintentionally read out a conversion result from a register
> while
> diff --git a/hw/tusb6010.c b/hw/tusb6010.c
> index d6847d0..3cf2e6c 100644
> --- a/hw/tusb6010.c
> +++ b/hw/tusb6010.c
> @@ -513,8 +513,7 @@ static void tusb_async_writew(void *opaque,
> target_phys_addr_t addr,
> s->dev_config = value;
> s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
> if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
> - cpu_abort(cpu_single_env, "%s: Product Test mode not
> allowed\n",
> - __FUNCTION__);
> + hw_error("%s: Product Test mode not allowed\n",
> __FUNCTION__);
> break;
>
> case TUSB_PHY_OTG_CTRL_ENABLE:
> diff --git a/hw/usb-musb.c b/hw/usb-musb.c
> index 8e1e6eb..adc76a2 100644
> --- a/hw/usb-musb.c
> +++ b/hw/usb-musb.c
> @@ -556,7 +556,7 @@ static int musb_timeout(int ttype, int speed,
> int val)
> /* TODO: what with low-speed Bulk and Isochronous? */
> }
>
> - cpu_abort(cpu_single_env, "bad interval\n");
> + hw_error("bad interval\n");
> }
>
> static inline void musb_packet(struct musb_s *s, struct musb_ep_s *ep,
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread