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Message-ID: <4A4AB845.1030906@caviumnetworks.com>
Date:	Tue, 30 Jun 2009 18:13:41 -0700
From:	David Daney <ddaney@caviumnetworks.com>
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To:	"Maciej W. Rozycki" <macro@linux-mips.org>
CC:	Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Define  __arch_swab64 for all mips r2 cpus (v2).
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Maciej W. Rozycki wrote:
> On Mon, 29 Jun 2009, Ralf Baechle wrote:
> 
>>> Some CPUs implement mipsr2, but because they are a super-set of
>>> mips64r2 do not define CONFIG_CPU_MIPS64_R2.  Cavium OCTEON falls into
>>> this category.  We would still like to use the optimized
>>> implementation, so since we have already checked for
>>> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
>>> CONFIG_CPU_MIPS64_R2 is sufficient.
>>>
>>> Change from v1: Add comments about why the change is safe.
>> Thanks, applied.  Though this sort of patch make me thing that maybe we
>> rather should have treated the cnMIPS cores differently.
> 
>  This is a pure code generation option and it asks for "select 
> CPU_MIPS64_R2" under CPU_OCTEON (or whatever option is used for that 
> chip).  Or something like "select ISA_MIPS64_R2" actually, as we want to 
> keep CPU_foo as the -march=, etc. designator.  IOW it looks like we lack 
> ISA supersetting along the lines of how tools handle it.
> 

The problem with CPU_MIPS64_R2 in the kernel is that it means two 
unrelated things:

1) The cpu can execute all mips64r2 ISA instructions.

2) The cpu requires that all worse case cache and execution hazards are 
handled.

In the case of the Octeon processors, #1 is true, but we can get better 
performance by omitting many of the hazard barriers because they are 
unneeded.

David Daney