Re: [PATCH] ARM: OMAP3: allow setting cam_mclk rate

[Artem Bityutskiy <Artem.Bityutskiy@nokia.com>]

Hi Jouni,

could you please take a quick look at this patch? There is some
pressure to have this applied ASAP, but I'm afraid I do not have
enough competence in this area to review it. Could you take a
brief look and validate it?

Toivonen Tuukka.O (Nokia-D/Oulu) wrote:
> This patch allows drivers to modify cam_mclk rate which is
> used for generating external cam_xclka and cam_xclkb for cameras.
> 
> Signed-off-by: Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c |   18 ++++++++++++++++++
>  arch/arm/mach-omap2/clock34xx.h |    2 ++
>  2 files changed, 20 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 045da92..667a608 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -898,6 +898,24 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
>  	return rate;
>  }
>  
> +/* Clock control for OMAP3 camera */
> +
> +static int omap3_cam_mclk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	const unsigned int dpll4_rate = 864000000; /* Hz */
> +	int clksel;
> +
> +	if (rate <= 0)
> +		return -EINVAL;
> +
> +	clksel = (dpll4_rate + (rate>>1)) / rate;
> +	clksel = clamp(clksel, 1, 16);
> +	cm_write_mod_reg(clksel, OMAP3430_CAM_MOD, CM_CLKSEL);
> +	clk->rate = dpll4_rate / clksel;
> +
> +	return 0;
> +}
> +
>  /* Common clock code */
>  
>  /*
> diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
> index e433aec..bd09709 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -37,6 +37,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk);
>  static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
>  static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
>  static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
> +static int omap3_cam_mclk_set_rate(struct clk *clk, unsigned long rate);
>  
>  /* Maximum DPLL multiplier, divider values for OMAP3 */
>  #define OMAP3_MAX_DPLL_MULT		2048
> @@ -2342,6 +2343,7 @@ static struct clk uart3_fck = {
>  	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
>  	.clkdm_name	= "per_clkdm",
>  	.recalc		= &followparent_recalc,
> +	.set_rate	= &omap3_cam_mclk_set_rate,
>  };
>  
>  static struct clk gpt2_fck = {


-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
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